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APPLICATION INFORMATION

Theory of Operation

Input Configuration

R

50

0

W

Z

50

0

W

ADS5463

AIN

AIN

S0176-03

R

200 W

ACSignal

Source

Mini-Circuits

JTX-4-10T

ADS5463

SLAS515 – NOVEMBER 2006

The ADS5463 is a 12-bit, 500-MSPS, monolithic-pipeline, analog-to-digital converter. Its bipolar analog core

operates from 5-V and 3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs.

The conversion process is initiated by the rising edge of the external input clock. At that instant, the differential

input signal is captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a

series of lower resolution stages, with the outputs combined in a digital correction logic block. Both the rising and

the falling clock edges are used to propagate the sample through the pipeline every half clock cycle. This

process results in a data latency of 3.5 clock cycles, after which the output data is available as a 12-bit parallel

word, coded in offset binary format.

The analog input for the ADS5463 consists of an analog pseudodifferential buffer followed by a bipolar transistor

track-and-hold. The analog buffer isolates the source driving the input of the ADC from any internal switching.

The input common mode is set internally through a 500-

Ω resistor connected from 2.4 V to each of the inputs.

This results in a differential input impedance of 1 k

Ω.

For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swings

symmetrically between 2.4 V + 0.55 V and 2.4 V – 0.55 V. This means that each input has a maximum signal

swing of 1.1 Vpp for a total differential input signal swing of 2.2 Vpp. The maximum swing is determined by the

internal reference voltage generator, eliminating the need for any external circuitry for this purpose.

The ADS5463 obtains optimum performance when the analog inputs are driven differentially. The circuit in

Figure 36 shows one possible configuration using an RF transformer with termination either on the primary or on

the secondary of the transformer. In addition, the evaluation module is configured with two back-to-back

transformers, which also demonstrates good performance. If voltage gain is required, a step-up transformer can

be used.

Besides the transformer configurations, Texas Instruments offers a wide selection of single-ended operational

amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as Texas

Instruments' THS9001, can also be used for high-input-frequency applications. For large voltage gains at

intermediate-frequencies in the 50-MHz–500-MHz range, the configuration shown in Figure 37 can be used. The

component values can be tuned for different intermediate frequencies. The example shown is located on the

evaluation module and is tuned for an IF of 170 MHz. More information regarding this configuration can be found

in the ADS5463 EVM User Guide (SLAU194) and the THS9001 50 MHz to 350 MHz Cascadeable Amplifier data

sheet (SLOS426).

Figure 36. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer

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