Pin Descriptions

PIN NUMBER

PIN NAME

1,36,43,48,56

VDDL

2

IOAPIC

3,11,16,21,

29,37,42,49,

GND

52

4

X1

5

X2

6

AVDD

7

FS02• 3

REF0

8,17,22,27

VDD

9

FS12'3

AGP0

10

AGP1

12

PCICLK F

FS21'2

20,19,18,15,

PCICLK(5:0)

14,13

23

PCICLK6

24

PCI_STOP#

25

CPU_STOP#

PD#

26

Vtt_PWRGD

28

FS32• 3

48MHz

30

SDATA

31

SCLK

33,35,39,41,

DDRT(6:0)

45,47,51

32,34,38,40,

DDRC(6:0)

44,46,50

53,54

CPUCLK(1:0)

55

CPUCLK F

Notes:

TYPE

PWR

OUT

PWR

IN

OUT

PWR

IN

OUT

PWR

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN

OUT

1/0

IN

OUT

OUT

OUT

OUT

DESCRIPTION

Power supply pins,nominal 2.5V

2.5V clock outputs

Ground pins

Crystal input.nominally 14.318MHz.

Crystal output,nominally 14.318MHz.

Analog power supply for 3.3V

Frequency select pin.

14.318 MHz reference clock.

Power supply pins,nominal 3.3V

Frequency select pin.

AGP outputs defined as 2X PCI.

AGP output defined as 2X PCI.

Free running PCI clock

Frequency select pin.

PCI clock outputs.

ICS951702

Advance Information

PCI clock output(selectable 1X or 2X via 12C)

Stops all PCICLKs at logic 0 level,when input low besides the

PCICLK_F clocks which are controllable by 12C bits whether they are

free runnina or stoooed bv PCI STOP.

Stops all CPUCLKs at logic 0 level,when input low. The individual

CPU clocks are controllable by 12c bits whether they are free

running or stopped by CPU STOP.

Asynchronous active low input pin used to power down the device

into a low power state. The internal clocks are disabled and the

VCO and the crystal are stopped. The latency of the power down will

not be areater than 3ms.

This pin acts as a dual function input pin for Vtt_PWRGD and PD#

signal. When Vtt_PWRGD goes high the frequency select will be

latched at power on thereafter the pin is an asynchronous active low

I power down oin.

Frequency select pin

48MHz output clock

Data oin for 12C circuitrv 5V tolerant

Clock oin of 12c circuitrv 5V tolerant

''True" clocks of differential pair DDR SDRAM outputs - 2.5V

"Complementry" clocks of differential pair

DDR SDRAM outputs - 2.5V

2.5V CPU clocks

Free runnina CPU clock. Not affected by the CPU STOP#.

1:

Internal Pull-up Resistor of 120K to 3.3V on indicated inputs

2:

Internal pull-down resistor of 120K to GND on indicated inputs.

3:

Bidirectional inpuUoutput pins, input logic levels are latched at internal power-on-reset. Use

1OKohm resistor to program logic Hi to VDD or GND for logic low.

0664-07/29/02

2