ICS951703

Third party brands and names are the property of their respective owners.

Block Diagram

Recommended Application:

Mobile applications

Output Features:

•

3 CPU (2.5V) (100MHz)

•

7 SDRAM (3.3V) (1 free running SDCLK) (100MHz)

•

7 PCI (3.3 V) @ 33.3MHz, (1 free running)

•

2 IOAPIC (2.5V) @ 33.3 MHz

•

2 (3.3V) @ 48 MHz

- 1 USB clock (3.3V) (48MHz non-SSC)

- 1 DOT clock (3.3V) (48MHz non-SSC)

•

1 VCH clock (3.3V) 48 MHz non-SSC,

or 66 MHz CPU-SSC

•

3 3V66 (3.3V) (66MHz)

•

1 REF (3.3V) @ 14.318 MHz

Features:

•

Supports spread spectrum modulation,

0 to -0.5% down spread.

•

Support power management: PCI_STOP#,

CPU_STOP# and power down Mode

•I

2C interface for clock output control

Skew Specifications:

•

CPU-CPU <150psec

•

PCI-PCI <500psec

•

SDRAM-SDRAM <250psec

•

CPU-SDRAM <350psec

•

CPU-PCI 1-4nsec

•

CPU-3V66 1-4nsec

Functionality

Pin Configuration

56-Pin 300-mil SSOP and TSSOP

REF

VDDREF

X1

X2

GND

GND

3V66-0

3V66-1

3V66-2

VDD3V66

PCI_STOP#

PCICLK_F

PCICLK1

GND

PCICLK2

PCICLK3

VDDPCI

PCICLK4

PCICLK5

PCICLK6

GND

AVDD

AGND

GND

48MHz_1

48MHz_2

VDD48

FS0

GND

IOPAIC-0

IOAPIC-1

VDDL

CPU0

VDDL

CPU1

CPU2

GND

GND

SDRAM0

SDRAM1

VDDSDR

SDRAM2

SDRAM3

GND

SDRAM4

SDRAM5

SDRAM_F

VDDSDR

VCH_CLK

VDD

CPU_STOP#

FS2

PD#

SCLK

SDATA

FS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Power Groups

VDD48= 48MHz, PLL2

AVDD = Analog VDD for CPU PLL

VDDREF = REF, Xtal Osc.

PLL2

PLL1

Spread

Spectrum

48MHz (2:1)

CPUCLK 0

SDRAM (5:0)

IOAPIC (1:0)

VCH_CLK

PCICLK (6:1)

SDRAM_F

CPUCLK (2:1)

PCICLK_F

3V66 (2:0)

3

7

2

6

2

2

X1

X2

XTAL

OSC

CPU

DIVDER

SDRAM

DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

I2C

Stop

Stop

Stop

Control

Logic

Config.

Reg.

REF

SDATA

SCLK

FS (2:0)

PD#

PCI_STOP#

CPU_STOP#

2

S

F1

S

F0

S

Fn

o

i

t

c

n

u

F

0X

0

e

t

a

t

s

i

r

T

0X

1

t

s

e

T

10

1

z

H

M

0

0

1

=

U

P

C

e

v

i

t

c

A

z

H

M

0

0

1

=

M

A

R

D

S