ICS954201 datasheet(13/17 Pages) RENESAS

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ICS954201

0819H—02/17/06

SMBus Table: Test and Readback Control Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

Test Mode Selection

Hi-Z

REF/N

Bit 6

Test Clock Mod eEntry

Test Mode

Disable

Enable

Bit 5

Bit 4

REFOUT STRENGTH

Strength Prog

Bit 3

PCI/SRC_STOP

Stop all PCI and SRC

clocks

Enabled

Disabled

Bit 2

FS_C

readback

LATCHED

Bit 1

FS_B

readback

LATCHED

Bit 0

FS_A

readback

LATCHED

SMBus Table: Vendor & Revision ID Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

RID3

Bit 6

RID2

Bit 5

RID1

Bit 4

RID0

Bit 3

VID3

Bit 2

VID2

Bit 1

VID1

Bit 0

VID0

RESERVED

VENDOR ID

Byte 7

REVISION ID

Byte 6

Test Clarification Table

Comments

FS_C/TEST

_SEL

HW PIN

FS_B/TEST

_MODE

HW PIN

TEST

ENTRY

BIT

B6b6

REF/N or

HI-Z

B6b7

OUTPUT

NORMAL

HI-Z

REF/N

HI-Z

REF/N

B6b6: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)

B6b7: 1= REF/N, Default = 0 (HI-Z)

· FS_C/TEST_SEL is a 3-level latched input.

o Power-up w/ V >= 2.0V to select TEST

o Power-up w/ V < 2.0V to have pin function as

FS_C.

· When pin is FS_C, VIH_FS and VIL_FS levels

apply.

· FS_B/TEST_MODE is a low-threshold input

o VIH_FS and VIL_FS levels apply.

o TEST_MODE is a real time input

· TEST_SEL can be invoked after power up

through SMBus B6b6.

o If TEST is selected by B6b6, only B6b7 controls

TEST_MODE. The FS_B/TEST_Mode pin is not

used.

· Power must be cycled to exit TEST.

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