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EPE6104 Datasheet(PDF) 2 Page - PCA ELECTRONICS INC. |
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EPE6104 Datasheet(HTML) 2 Page - PCA ELECTRONICS INC. |
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2 / 2 page ![]() The circuit below is a guideline for interconnecting PCA’s EPE6104 with NSC DP83950B Repeater/10 Base-T PHY chip over UTP cable. Further details of system design, such as chip pin-out, etc. can be obtained from the specific chip manufacturer. Typical insertion loss of the isolation transformer/filter is 0.7dB. This parameter covers the entire spectrum of the encoded signals in 10 Base-T protocols. However, the predistortion resistor network introduces some loss which has to be taken into account in determining how well your design meets the Standard Template requirements. Additionally, note that NSC suggests using a set of resistor networks with lower values suitable for more optimum voltage level control. Users can obtain modules with either values from PCA (EPE6092). But please check with NSC to find which set suits most for your specific application. EPE6104 has the lower values. Effective termination impedance offered by the outputs of the transmit channel is 2*(62//303)//800 Ω or approximately 92Ω. Thus, bench testing of return loss needs to add approx. 7.5 Ω on each leg of the transmit inputs to take into account the 74ACTXXXX output impedance. Note that some systems have auto polarity detection and some do not. If not, be certain to follow the proper polarity. It is recommended that system designers ground the chip side center taps via a low voltage capacitor. Taking the cable side center taps to chassis via capacitors, is not recommended, as this will add cost without containing EMI. This may worsen EMI, specifically if the primary “common mode termination” is pulled to ground as shown. The pull down resistors used around the RJ45 connector have been known to suppress unwanted radiation that unused wires pick up from the immediate environment. Their placement and use are to be considered carefully before a design is finalized. It is recommended that there be a neat separation of ground planes in the layout. It is generally accepted practice to limit the plane off at least 0.08 inches away from the chip side pins of EPE6104. There need not be any ground plane beyond this point. For best results, PCB designer should design the outgoing traces preferably to be 50 Ω, balanced and well coupled to achieve minimum radiation from these traces. CSE6104b Rev. - 10/24/96 10 Base-T Interface Module for Multiport Applications Typical Application Circuit (for one port only) E L E C T R O N I C S I N C . Notes : * Pin-outs shown are for Hub/Repeater Applications only. EPE6104 DP83950B PHY RJ45 3 6 2 1 TX+ TXd+ RX+ RX- EPE6104 TX+ TX- RX+ RX- TX- TXd- Chassis Ground 8 7 45 8 6 11 9 2 1 4 3 14 16 7 TEL: (818) 892-0761 FAX: (818) 894-5791 http://www.pca.com PCA ELECTRONICS, INC. 16799 SCHOENBORN ST. NORTH HILLS, CA 91343 |
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