LTC4260IGN datasheet(16/28 Pages) LINER

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LTC4260

4260f

The SOA (safe operating area) curves of candidate FETs

must be evaluated to ensure that the heat capacity of the

package can stand 24W for 16ms. The SOA curves of the

Fairchild FDB3632 provide for 1A at 50V (50W) for 10ms,

satisfying the requirement.

The inrush current is set to 1A using C1:

GATE UP

INRUSH

10 33

()

Default values of R5 = 10Ω and R6 = 100k are chosen as

discussed previously.

The power dissipated in the FET during overcurrent must

be limited. The active current limit uses a timer to prevent

excessive energy dissipation in the FET. The worst-case

power occurs when the voltage versus current profile of

the foldback current limit is at the maximum. This occurs

when the current is 5A and the voltage is 1/2 of the 48V or

24V. See the Current Limit Sense Voltage vs FB Voltage in

the Typical Performance curves to view this profile. In

order to survive 120W, the FET SOA curve dictates the

maximum time at this power level. This particular FET

allows 300W at 1ms or less. Therefore, it is acceptable to

set the current limit timeout using CT to be 0.81ms:

ms F

T =

[]

081

Note the minimum value for CT is 0.1nF.

Choose R1, R2, R3, R7 and R8 for the UV, OV and PG

threshold voltages:

VOVRISING = 71.2V, VOVFALLING = 69.44V (using VOV(TH) =

3.5V rising and 3.41V falling)

VUVRISING = 43V, VUVFALLING = 38.5V, (using VUV(TH) =

3.5V rising and 3.12V falling)

VPGRISING = 46.14V, VPGFALLING = 45V, (using VFB = 3.5V

rising and 3.411V falling)

In addition a 0.1µF ceramic bypass capacitor is placed on

the INTVCC pin. The complete circuit is shown in Figure 1.

Layout Considerations

To achieve accurate current sensing, a Kelvin connection

is recommended. The minimum trace width for 1oz cop-

per foil is 0.02" per amp to make sure the trace stays at a

reasonable temperature. Using 0.03" per amp or wider is

recommended. Note that 1oz copper exhibits a sheet

resistance of about 530µΩ/ . Small resistances add up

quickly in high current applications. To improve noise

immunity, put the resistive divider to the UV, OV and FB

pins close to the device and keep traces to VDD and GND

short. It is also important to put C3, the bypass capacitor

for the INTVCC pin, as close as possible between INTVCC

and GND. A 0.1µF capacitor from the UV pin (and OV pin

through resistor R2) to GND also helps reject supply

noise. Figure 5 shows a layout that addresses these

issues. Note that a surge suppressor, Z1, is placed be-

tween supply and ground using wide traces.

APPLICATIO S I FOR ATIO

SENSE

LTC4260

VDD

SENSE RESISTOR RS

ILOAD

VIN

GND

ILOAD

4260 F05

GND

INTVCC

Figure 5. Recommended Layout for

R1, R2, R3, R8, CF, C3, Z1 and RS

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