| Electronic Components Datasheet Search |
|
IDTCV146PVG Datasheet(PDF) 2 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
IDTCV146PVG Datasheet(HTML) 2 Page - Renesas Technology Corp |
|
2 / 17 page ![]() COMMERCIALTEMPERATURERANGE 2 IDTCV146 PROGRAMMABLEFLEXPC™CLOCKFORP4PROCESSOR PIN CONFIGURATION Symbol Description Min Max Unit VDDA 3.3V Core Supply Voltage 4.6 V VDD 3.3V Logic Input Supply Voltage GND - 0.5 4.6 V TSTG Storage Temperature –65 +150 ° C TAMBIENT Ambient Operating Temperature 0 +70 ° C TCASE Case Temperature +115 ° C ESD Prot Input ESD Protection 2000 V Human Body Model ABSOLUTE MAXIMUM RATINGS(1) NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. SSOP TOP VIEW 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF0/FSC GND_REF XTAL_IN XTAL_OUT VDD_REF SDAT SCL CPU0 CPU0# VDD_CPU CPU1 CPU1# CPU_ITP#/SRC6# VDD_SRC SRC5 SRC5# GND_SRC SRC4# SRC3 SRC3# VDD_SRC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PCI0 PCI1 PCI3 PCI4 PCI5 GND_PCI VTT_PWRGD#/PD VDD48 USB48/FSB GND48 DOT96 DOT96# SRC1 SRC1# VDD_SRC SRC2 SRC2# SATA_SRC SATA_SRC# SRC4 GND_PCI VDD_PCI PCI2 VDD_PCI *TEST_SEL/PCIF0 ITP_EN/PCIF1 SRC0 SRC0# GND_SRC CPU_ITP/SRC6 REF1/FSA GND_CPU IREF GND_A VDD_A FREQUENCY SELECTION TABLE FSC, B, A CPU Mode, MHz SATA_SRC SRC[5:0] PCI USB DOT96 REF 101 100 100 100 33.3 48 96 14.318 001 133 100 100 33.3 48 96 14.318 011 166 100 100 33.3 48 96 14.318 010 200 100 100 33.3 48 96 14.318 000 266 100 100 33.3 48 96 14.318 100 333 100 100 33.3 48 96 14.318 110 400 100 100 33.3 48 96 14.318 111 Reserve 100 100 33.3 48 96 14.318 ITP_EN pin 38 pin 39 1 CPUC2_ITP CPUT_ITP 0 SRCC6 SRCT6 TEST CLARIFICATION TABLE HW SW TEST_SEL/ TEST SELECT PCICLK_F0 BIT B6b6 OUTPUT Comments 0 0 Normal NormalOperation 1 X Hi-Z Power-up with TEST_SEL =1 to enter test mode. Cycle power with TEST_SEL=0todisabletestmode 0 1 Hi-Z If TEST_SEL HW pin is 0 during power-up,testmodecanbeinvoked through B6b6. Cycle power with TEST_SEL=0todisabletestmode. * = Internal pull down |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |