LM1771 datasheet(12/18 Pages) NSC

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Design Guide (Continued)

ofaC

FF capacitor is recommended as it improves the regu-

lation and stability of the design. However, its benefit is

diminished as V

OUT starts approaching VREF , therefore it is

not needed in this situation.

INPUT CAPACITOR

The dominating factor that usually sets an input capacitors’

size is the current handling ability. This is usually determined

by the package size and ESR of the capacitor. If these two

criteria are met then there usually should be enough capaci-

tance to prevent impedance interactions with the source. In

general it is recommended to use a ceramic capacitor for the

input as they provide a low impedance and small footprint.

One important note is to use a good dielectric for the ceramic

capacitor such as X5R or X7R. These provide better over

temperature performance and also minimize the DC voltage

derating that occurs on Y5V capacitors. To calculate the

input capacitor RMS current, the equation below can be

used:

which can be approximated by,

MOSFET Selection

The two FETs used in the LM1771 requires attention to

selection of parameters to ensure optimal performance of

the power supply. The high side FET should be a PFET and

the low side an NFET. These can be integrated in one

package or as two separate packages. The criteria that

matter in selection are listed below:

VDS VOLTAGE RATING

The first selection criteria is to select FETs that have suffi-

cient V

DS voltage ratings to handle the maximum voltage

seen at the input plus any transient spikes that can occur

from parasitic ringing. In general most FETs available for this

application will have ratings from 8V to 20V. If a larger

voltage rating is used then the performance will most likely

be degraded because of higher gate capacitance.

RDSON

The R

DS(ON) specification is important as it determines sev-

eral attributes of the FET and the overall power supply. The

first is that it sets the maximum current of the FET for a given

package. A lower R

DS(ON) will permit a higher allowable

current and reduce conduction losses, however, it will in-

crease the gate capacitance and the switching losses.

GATE DRIVE

The next step is to ensure that the FETs are capable of

switching at the low Vin supplies used by the LM1771. The

FET should have the Rdson specified at either 1.8V or 2.5V

to ensure that it can switch effectively as soon as the

LM1771 starts up.

GATE CHARGE

Because the LM1771 utilizes a fixed dead-time scheme to

prevent cross conduction, the FET transitions must occur in

this time. The rise and fall time of the FETs gate can be

influenced by several factors including the gate capacitance.

Therefore the total gate charge of both FETs should be

limited to less than 20nC at 4.5V V

GS. The lower the number

the faster the FETs should switch and the better the effi-

ciency.

RISE / FALL TIMES

A better indication of the actual switching times of the FETs

can be found in their electrical characteristics table. The rise

and fall time should be specified and selected to be at a

minimum. This helps improve efficiency and ensuring that

shoot through does not occur.

GATE CHARGE RATIO

Another consideration in selecting the FETs is to pay atten-

tion to the Qgd / Qgs ratio. The reason for this is that proper

selection can prevent spurious turn on. If we look at the

NFET for example, when the FET is turning off, the gate

signal will pull to ground. Conversely the PFET will be turn-

ing on, causing the SW node to rise towards V

IN. The gate to

drain capacitance of the NFET couples the SW node to the

gate and will cause it to rise. If this voltage is excessive, then

it could weakly turn on the low side FET causing an effi-

ciency loss. However, this coupling is mitigated by having a

large gate to source capacitance of the FET, which helps to

hold the gate voltage down. Ideally, a very low Qgd / Qgs

would be ideal, but in practice it is common to find the

number around 1. As a general rule, the lower the ratio, the

better.

If the above selection criteria have been met it is useful to

generate a figure of merit to allow comparison between the

FETs. One such method is to multiply the R

DS(ON) of the FET

by the total gate charge. This allows an easy comparison of

the different FETs available. Once again, the lower the prod-

uct, the better.

FEEDBACK RESISTORS

The feedback resistors are used to scale the output voltage

to the internal reference value such that the loop can be

regulated. The feedback resistors should not be made arbi-

trarily large as this creates a high impedance node at the

feedback pin that is more susceptible to noise. A combined

value of 50k

Ω for the two resistors is adequate. To calculate

the resistor values use the equation below. Typically the low

side resistor is initially set to a pre-determined value such as

10 k

Ω.

FB is the internal reference voltage that can be found in the

electrical characteristics table or approximated by 0.8V.

The output voltage value can be set in a precise manner by

taking into account the fact that the reference voltage is

regulating the bottom of the output ripple as opposed to the

average value. This relationship is shown in the figure below.

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