AD7980 datasheet(13/22 Pages) AD

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Preliminary Technical Data

AD7980

Rev Pr C | Page 13 of 22

VOLTAGE REFERENCE INPUT

The AD7980 voltage reference input, REF, has a dynamic, input

impedance and should therefore be driven by a low impedance

source with efficient decoupling between the REF and GND

pins, as explained in the Layout section.

When REF is driven by a very low impedance source, for

example, a reference buffer using the AD8031 or the AD8605, a

10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for

optimum performance.

If an unbuffered reference voltage is used, the decoupling value

depends on the reference used. For instance, a 22 μF (X5R,

1206 size) ceramic chip capacitor is appropriate for optimum

performance using a low temperature drift ADR43x reference.

If desired, smaller reference decoupling capacitor values down

to 2.2 μF can be used with a minimal impact on performance,

especially DNL.

Regardless, there is no need for an additional lower value

ceramic decoupling capacitor (for example, 100 nF) between the

REF and GND pins.

POWER SUPPLY

It uses two power supply pins: a core supply VDD and a digital

input/output interface supply VIO. VIO allows direct interface

with any logic between 1.8 V and VDD. To reduce the supplies

needed, the VIO and VDD can be tied together. The AD7980 is

independent of power supply sequencing between VIO and

VDD. Additionally, it is very insensitive to power supply

variations over a wide frequency range.

The AD7980 powers down automatically at the end of each

conversion phase and, therefore, the power scales linearly with

the sampling rate. This makes the part ideal for low sampling

rate (even a few Hz) and low battery-powered applications.

DIGITAL INTERFACE

Though the AD7980 has a reduced number of pins, it offers

flexibility in its serial interface modes.

The AD7980, when in CS mode, is compatible with SPI, QSPI,

digital hosts, and DSPs, e.g., Blackfin® ADSP-BF53x or ADSP-

219x. This interface can use either 3-wire or 4-wire. A 3-wire

interface using the CNV, SCK, and SDO signals minimizes

wiring connections useful, for instance, in isolated applications.

A 4-wire interface using the SDI, CNV, SCK, and SDO signals

allows CNV, which initiates the conversions, to be independent

of the readback timing (SDI). This is useful in low jitter

sampling or simultaneous sampling applications.

The AD7980, when in chain mode, provides a daisy chain

feature using the SDI input for cascading multiple ADCs on a

single data line similar to a shift register.

The mode in which the part operates depends on the SDI level

when the CNV rising edge occurs. The CS mode is selected if

SDI is high and the chain mode is selected if SDI is low. The

SDI hold time is such that when SDI and CNV are connected

together, the chain mode is always selected.

In either mode, the AD7980 offers the flexibility to optionally

force a start bit in front of the data bits. This start bit can be

used as a BUSY signal indicator to interrupt the digital host and

trigger the data reading. Otherwise, without a BUSY indicator,

the user must time out the maximum conversion time prior to

readback.

The BUSY indicator feature is enabled as:

• In the CS mode, if CNV or SDI is low when the ADC

conversion ends (Figure 18 and Figure 22).

• In the chain mode, if SCK is high during the CNV rising edge

(Figure 26).

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