AD5062/AD5063

Preliminary Technical Data

Rev. Pr B | Page 14 of 17

DB23

DB0

SCLK

SYNC

DIN

DB23

DB0

VALID WRITE SEQUENCE, OUTPUT UPDATES

INVALID WRITE SEQUENCE:

Figure 23. SYNC Interrupt Facility

AD5062/AD5063 to 68HC11/68L11 Interface

Figure 26 shows a serial interface between the AD5060 and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK of the AD5060, while the MOSI

output drives the serial data line of the DAC. The SYNC

signal is derived from a port line (PC7). The setup conditions

for correct operation of this interface are as follows: the

68HC11/68L11 should be configured so that its CPOL bit is a 0

and its CPHA bit is a 1. When data is being transmitted

to the DAC, the SYNC line is taken low (PC7). When the

68HC11/68L11 is configured as above, data appearing on the

MOSI output is valid on the falling edge of SCK. Serial data

from the 68HC11/68L11 is transmitted in 8-bit bytes with only

eight falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. In order to load data to the

AD5062/AD5063, PC7 is left low after the first eight bits are

transferred, and a second serial write operation is performed to

the DAC and PC7 is taken high at the end of this procedure.

Figure 26. AD5062/AD5063 to 68HC11/68L11 Interface

AD5062/AD5063 to Blackfin ADSP-BF53X

Interface

Figure 2X shows a serial interface between the AD5641 and the

Blackfin ADSP-53X microprocessor. The ADSP-BF53X processor

family incorporates two dual-channel synchronous serial ports,

SPORT1 and SPORT0 for serial and multiprocessor

communications. Using SPORT0 to connect to the AD5062/63, the

setup for the interface is as follows. DT0PRI drives the SDIN pin of

the AD5062/63, while TSCLK0 drives the SCLK of the part. The

SYNC is driven from TFS0.

Figure 2X. AD5062/AD5063 to Blackfin ADSP-BF53X

Interface

AD5062/AD5063 to 80C51/80L51 Interface

Figure 27 shows a serial interface between the AD5062/AD5063

and the 80C51/80L51 microcontroller. The setup for the

interface is as follows:TXDofthe80C51/80L51drivesSCLKofthe

AD5062/AD5063, while RXD drives the serial data line of the

part. The SYNC signal is again derived from a bit

programmable pin on the port. In this case port line P3.3 is

used. When data is to be transmitted to the AD5062/AD5063,

P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit

bytes; thus only eight falling clock edges occur in the transmit

cycle. To load data to the DAC, P3.3 is left low after the first

eight bits are transmitted, and a second write cycle is initiated

to transmit the second byte of data. P3.3 is taken high following

the completion of this cycle. The 80C51/80L51 outputs the

serial data in a format which has the LSB first. The

AD5062/AD5063 requires its data with the MSB as the first bit

received. The 80C51/80L51 transmit routine should take this

into account.

Figure 27. AD5062/AD5063 to 80C51/80L51 Interface

AD5062/AD5063 to Microwire Interface

Figure 28 shows an interface between the AD5062/AD5063 and

any microwire compatible device. Serial data is shifted out on

the falling edge of the serial clock and is clocked into the

AD5062/AD5063 on the rising edge of the SK.

Figure 28. AD5062/AD5063 to MICROWIRE Interface

APPLICATIONS

Choosing a Reference for the AD5062/AD5063.

To achieve the optimum performance from the AD5060,

thought should be given to the choice of a precision voltage