ADE7169F16 datasheet(84/140 Pages) AD

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ADE7169F16

Preliminary Technical Data

Rev. PrD | Page 84 of 140

0xC2

WDS

WDS Watchdog status bit.

This bit is set to indicate that a watchdog timeout has occurred.

WDS is cleared by writing a zero or by an external hardware reset. A watchdog

reset will not clear WDS. The bit can therefore be used to distinguish between a

watchdog reset and a hardware reset from the RESET pin.

0xC1

WDE

WDE Watchdog enable bit.

When set, enables the watchdog and clears its counter (e.g. 2 above). The

watchdog counter is subsequently cleared again whenever the WDE bit is set. If

the watchdog is not cleared within its selected timeout period it will generate a

system reset or watchdog interrupt, depending on the WDIR bit. The watchdog is

disabled (and WDE cleared) by any of the following:

Write zero to WDE

Watchdog reset (WDIR = 0)

Hardware reset

PSM interrupt

LOCK interrupt.

0xC0

WDWR

WDWR Watchdog write enable bit. To write data into the WDCON SFR involves a

double instruction sequence. The WDWR bit must be set and the following

instruction must be a write instruction to the WDCON SFR. This sequence is

necessary so that the WDCON SFR is protected from code execution upsets that

might unintentionally modify this SFR. Interrupts should be disabled during this

operation due to the consecutive instruction cycles.

e.g. Disable Watch dog

1 write to WDCON e.g. 2 Clear WDE bit

CLR EA

SETB WDWR

CLR WDE

SETB EA

INTERRUPT PRIORITY

If two interrupts of the same priority level occur simultaneously, the polling sequence, as shown in

Table 66, is observed.

Table 66. Priority within Interrupt Level

Source

Priority

Description

IPSM

0 (Highest)

Power Supply Monitor Interrupt

IRTC

RTC Interval Timer interrupt

IADE

ADE Energy measurement interrupt

WDT

Watchdog Timer Overflow Interrupt

ITEMP

Temperature ADC interrupt

IE0

External Interrupt 0

TF0

Timer/Counter 0 Interrupt

IE1

External Interrupt 1

TF1

Timer/Counter 1 Interrupt

ISPI/I2CI

SPI/I2C Interrupt

RI/TI

UART Serial Port Interrupt

TF2/EXF2

11 (Lowest)

Timer/Counter 2 Interrupt

INTERRUPT FLAGS

The interrupt and status flags associated with the interrupt vectors are shown in Table 67 and Table 68. Most of the interrupts have flags

associated with them.

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