ADG791A/ADG791G

Rev. 0 | Page 10 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

1

S1A

2

S1B

3

D1

4

D2

5

S2B

6

S2A

15 NC

16 NC

17 NC

18 A2

14 NC

13 NC

ADG791A

TOP VIEW

(Not to Scale)

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD MUST BE TIED TO GND.

PIN 1

INDICATOR

1

S1A

2

S1B

3

D1

4

D2

5

S2B

6

S2A

15 NC

16 GPO1

17 NC

18 A2

14 NC

13 NC

ADG791G

TOP VIEW

(Not to Scale)

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD MUST BE TIED TO GND.

Figure 3. ADG791G Pin Configuration

Figure 4. ADG791A Pin Configuration

Table 5. ADG791A/ADG791G Pin Function Descriptions

Pin No.

Mnemonic

Description

1

S1A

A-Side Source Terminal for Mux 1. Can be an input or output.

2

S1B

B-Side Source Terminal for Mux 1. Can be an input or output.

3

D1

Drain Terminal for Mux 1. Can be an input or output.

4

D2

Drain Terminal for Mux 2. Can be an input or output.

5

S2B

B-Side Source Terminal for Mux 2. Can be an input or output.

6

S2A

A-Side Source Terminal for Mux 2. Can be an input or output.

7

S3A

A-Side Source Terminal for Mux 3. Can be an input or output.

8

S3B

B-Side Source Terminal for Mux 3. Can be an input or output.

9

D3

Drain Terminal for Mux 3. Can be an input or output.

10

D4

Drain Terminal for Mux 4. Can be an input or output.

11

S4B

B-Side Source Terminal for Mux 4. Can be an input or output.

12

S4A

A-Side Source Terminal for Mux 4. Can be an input or output.

13

NC

Not Internally Connected.

14

NC

Not Internally Connected.

15

NC

Not Internally Connected.

16

NC/GPO1

Not Internally Connected for ADG791A/General-Purpose Logic Output 1 for ADG791G.

17

NC

Not Internally Connected.

18

A2

Logic Input. Sets Bit A2 from the least significant bit of the 7-bit slave address.

19

A1

Logic Input. Sets Bit A1 from the least significant bit of the 7-bit slave address.

20

A0

Logic Input. Sets Bit A0 from the least significant bit of the 7-bit slave address.

21

SCL

Digital Input, Serial Clock Line. Open-drain input that is used in conjunction with SDA to clock data into

the device. External pull-up resistor required.

22

SDA

Digital I/O. Bidirectional, open-drain data line. External pull-up resistor required.

23

Positive Power Supply Input.

24

GND

Ground (0 V) Reference.