ADG792A/ADG792G

Rev. 0 | Page 10 of 24

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD

MUST BE TIED TO GND.

PIN 1

INDICATOR

1

S1A

2

S1B

3

D1

4

S1D

5

S1C

6

NC

15 D3

16 S3D

17 S3C

18 A2

14 S3B

13 S3A

ADG792A

TOP VIEW

(Not to Scale)

Figure 3. ADG792A Pin Configuration

PIN 1

INDICATOR

1

S1A

2

S1B

3

D1

4

S1D

5

S1C

6

GPO2

15 D3

16 S3D

17 S3C

18 A2

14 S3B

13 S3A

ADG792G

TOP VIEW

(Not to Scale)

NOTES

1. THE EXPOSED PAD

MUST BE TIED TO GND.

Figure 4. ADG792G Pin Configuration

Table 5. Pin Function Descriptions

Pin

Mnemonic

No.

ADG792A/ADG792G

Function

1

S1A

A Side Source Terminal for Mux 1. Can be an input or output.

2

S1B

B Side Source Terminal for Mux 1. Can be an input or output.

3

D1

Drain Terminal for Mux 1. Can be an input or output.

4

S1D

D Side Source Terminal for Mux 1. Can be an input or output.

5

S1C

C Side Source Terminal for Mux 1. Can be an input or output.

6

NC/GPO2

Not internally connected for ADG792A/General-Purpose Logic Output 2 for ADG792G.

7

S2A

A Side Source Terminal for Mux 2. Can be an input or output.

8

S2B

B Side Source Terminal for Mux 2. Can be an input or output.

9

D2

Drain Terminal for Mux 2. Can be an input or output.

10

S2D

D Side Source Terminal for Mux 2. Can be an input or output.

11

S2C

C Side Source Terminal for Mux 2. Can be an input or output.

12

NC/GPO1

Not internally connected for ADG792A/General-Purpose Logic Output 1 for ADG792G.

13

S3A

A Side Source Terminal for Mux 3. Can be an input or output.

14

S3B

B Side Source Terminal for Mux 3. Can be an input or output.

15

D3

Drain Terminal for Mux 3. Can be an input or output.

16

S3D

D Side Source Terminal for Mux 3. Can be an input or output.

17

S3C

C Side Source Terminal for Mux 3. Can be an input or output.

18

A2

Logic Input. Sets Bit A2 from the least significant bits of the 7-bit slave address.

19

A1

Logic Input. Sets Bit A1 from the least significant bits of the 7-bit slave address.

20

A0

Logic Input. Sets Bit A0 from the least significant bits of the 7-bit slave address.

21

SCL

Digital Input, Serial Clock Line. Open-drain input that is used in conjunction with SDA to clock data into the

device. External pull-up resistor required.

22

SDA

Digital Input/Output. Bidirectional open-drain data line. External pull-up resistor required.

23

Positive Power Supply Input.

24

GND

Ground (0 V) Reference.