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AN2533 Datasheet(PDF) 15 Page - Motorola, Inc |
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AN2533 Datasheet(HTML) 15 Page - Motorola, Inc |
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15 / 24 page ![]() AN2533/D Detailed Function Description MOTOROLA Standard SVM – 3 outputs version – XOR version TPU Function Set (svmStd3Xor) 15 TPU function svmStd3Xor_sync generates an interrupt after each low to high transition. Host Service Bits (HSR) 00 – No Host Service Request 01 – Not used 10 – Initialization 11 – Not used Host Sequence Bits (HSQ) xx – Not used Channel Interrupt Enable 0 – Channel Interrupt Disabled 1 – Channel Interrupt Enabled Channel Interrupt Status 0 – Interrupt Not Asserted 1 – Interrupt Asserted Table 11. svmStd3Xor_sync Parameter RAM Channel Parameter 15 14 13 12 11 10 98 765 4321 0 0 move 1 pw 2 prescaler 3 presc_copy 4 time 5 dec 6 T_copy 7 Table 12. svmStd3Xor_sync parameter description Parameter Format Description Parameters written by CPU move 16-bit signed integer The number of TCR1 TPU cycles to forego (negative) or come after (positive) the PWM period center time pw 16-bit unsigned integer Synchronization pulse width in number of TCR1 TPU cycles. Table 10. svmStd3Xor_sync Control Bits Name Options 1 0 1 0 0 0 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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