ADN2928

Preliminary Technical Data

Rev. PrB | Page 8 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A

B

C

D

E

F

G

1 23 45 6 7

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Type1

Description

A1, A4, B5, B6, D3 to D6, E3,

F2, F6, G4, G7

GND

P

Ground

A7, C6, D7, E5, E6, F7

VDDT_1.8

P

1.8 V transmitter power supply

B1, C2, C3, D1, E4, G1

VDDR_1.8

P

1.8 V receiver power supply

C1, E7

VDD_3.3

P

3.3 V power supply

A2

RxINN

AI

Negative Differential Rx Data Input

A3

RxINP

AI

Positive Differential Rx Data Input

A5

TxOUTP

AO

Positive Differential Tx Data Output; CML

A6

TxOUTN

AO

Negative Differential Tx Data Output; CML

B2

RxTHR

AI

Receiver LOS Threshold Setting Resistor

B3

COSR

AO

Receiver Offset Compensation Loop Capacitor

B4

CVDD_1.0

P

100 nF Decoupling Capacitor for Internal 1 V digital supply

B7

NC

No Connect

C4

REFCLKN

AI

Negative Differential Reference Clock Input

C5

REFCLKP

AI

Positive Differential Reference Clock Input

C7

CFT

AO

Transmitter FLL Loop Filter Capacitor

D2

RxLOS

DO

Receiver Loss of Signal Alarm Output. Active High

E1

CFR

AO

Receiver FLL Loop Filter Capacitor

E2

PDN

DI

Chip Power Down Input

F1

CDR_NR

DO

CDR Not Ready Alarm. Active High.

F3

SDA

DI/O

F4

SCK

DI

F5

COST

AO

Transmitter Offset Compensation Loop Capacitor

G2

RxOUTN

AO

Negative Differential Rx Data Output; CML

G3

RxOUTP

AO

Positive Differential Rx Data Output; CML

G5

TxINN

AI

Negative Differential Tx Data Input

G6

TxINP

AI

Postive Differential Tx Data Input