MC68340 datasheet(302/441 Pages) FREESCALE

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MOTOROLA

MC68340 USER’S MANUAL

7- 7

7.2.9.1

RTSB. When used for this function, this signal can be programmed to be

automatically negated and asserted by either the receiver or transmitter. When connected

to the

CTS

≈ input of a transmitter, this signal can be used to control serial data flow.

7.2.9.2 OP1. When used for this function, this output is controlled by bit 1 in the OP.

7.2.10 Channel A Clear-To-Send (

CTSA)

This active-low input is the channel A clear-to-send.

7.2.11 Channel B Clear-To-Send (

CTSB)

This active-low input is the channel B clear-to-send.

7.2.12 Channel A Transmitter Ready (

≈RDYA)

This active-low output signal is programmable as the channel A transmitter ready or as a

dedicated parallel output, and cannot be masked by the interrupt enable register (IER).

7.2.12.1

≈RDYA. When used for this function, this signal reflects the complement of the

status of bit 2 of the channel A status register (SRA). This signal can be used to control

parallel data flow by acting as an interrupt to indicate when the transmitter contains a

character.

7.2.12.2 OP6. When used for this function, this output is controlled by bit 6 in the OP.

7.2.13 Channel A Receiver Ready (

≈RDYA)

This active-low output signal is programmable as the channel A receiver ready, channel A

FIFO full indicator, or a dedicated parallel output, and cannot be masked by the IER.

7.2.13.1

≈RDYA. When used for this function, this signal reflects the complement of the

status of bit 1 of the ISR. This signal can be used to control parallel data flow by acting as

an interrupt to indicate when the receiver contains a character.

7.2.13.2

FFULLA. When used for this function, this signal reflects the complement of the

status of bit 1 of the ISR. This signal can be used to control parallel data flow by acting as

an interrupt to indicate when the receiver FIFO is full.

7.2.13.3 OP4. When used for this function, this output is controlled by bit 4 in the OP.

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