MC68340 datasheet(298/441 Pages) FREESCALE

298 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

7- 3

7.1.1 Serial Communication Channels A and B

Each communication channel provides a full-duplex asynchronous/synchronous receiver

and transmitter using an operating frequency independently selected from a baud rate

generator or an external clock input.

The transmitter accepts parallel data from the IMB, converts it to a serial bit stream,

inserts the appropriate start, stop, and optional parity bits, then outputs a composite serial

data stream on the channel transmitter serial data output (TxDx). Refer to 7.3.2.1

Transmitter for additional information.

The receiver accepts serial data on the channel receiver serial data input (RxDx), converts

it to parallel format, checks for a start bit, stop bit, parity (if any), or break condition, and

transfers the assembled character onto the IMB during read operations. Refer to 7.3.2.2

Receiver for additional information.

7.1.2 Baud Rate Generator Logic

The crystal oscillator operates directly from a 3.6864-MHz crystal connected across the

X1 input and the X2 output or from an external clock of the same frequency connected to

X1. The clock serves as the basic timing reference for the baud rate generator and other

internal circuits.

The baud rate generator operates from the oscillator or external TTL clock input and is

capable of generating 19 commonly used data communication baud rates ranging from 50

to 76.8k by producing internal clock outputs at 16 times the actual baud rate. Refer to 7.2

Serial Module Signal Definitions and 7.3.1 Baud Rate Generator for additional

information.

The external clock input (SCLK), which bypasses the baud rate generator, provides a

synchronous clock mode of operation when used as a divide-by-1 clock and an

asynchronous clock mode when used as a divide-by-16 clock. The external clock input

allows the user to use SCLK as the only clock source for the serial module if multiple baud

rates are not required.

7.1.3 Internal Channel Control Logic

The serial module receives operation commands from the host and, in turn, issues

appropriate operation signals to the internal serial module control logic. This mechanism

allows the registers within the module to be accessed and various commands to be

performed. Refer to 7.4 Register Description and Programming for additional

information.

7.1.4 Interrupt Control Logic

Seven interrupt request (

IRQ7–IRQ1) signals are provided to notify the CPU32 that an

interrupt has occurred. These interrupts are described in 7.4 Register Description and

Programming. The interrupt status register (ISR) is read by the CPU32 to determine all

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68340 Datasheet(PDF) 298 Page - Freescale Semiconductor, Inc

MC68340 Datasheet(HTML) 298 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL