MC68340 datasheet(200/441 Pages) FREESCALE

200 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

5- 63

⇒

STATUS REGISTER

+$02

NEXT INSTRUCTION PROGRAM COUNTER HIGH

NEXT INSTRUCTION PROGRAM COUNTER LOW

+$06

1100

VECTOR OFFSET

+$08

FAULTED ADDRESS HIGH

FAULTED ADDRESS LOW

+$0C

PRE-EXCEPTION STATUS REGISTER

FAULTED EXCEPTION FORMAT/VECTOR WORD

+$10

FAULTED INSTRUCTION PROGRAM COUNTER HIGH (SIX WORD FRAME ONLY)

FAULTED INSTRUCTION PROGRAM COUNTER LOW (SIX WORD FRAME ONLY)

+$14

INTERNAL TRANSFER COUNT REGISTER

+$16

SPECIAL STATUS WORD

Figure 5-17. Format $C—Four- and Six-Word BERR Stack

5.6 DEVELOPMENT SUPPORT

All M68000 family members have the following special features that facilitate applications

development.

Trace on Instruction Execution—All M68000 processors include an instruction-by-

instruction tracing facility to aid in program development. The MC68020, MC68030, and

CPU32 can also trace those instructions that change program flow. In trace mode, an

exception is generated after each instruction is executed, allowing a debugger program to

monitor execution of a program under test. See 5.5.2.10 Tracing for more information.

Breakpoint Instruction—An emulator can insert software breakpoints into target code to

indicate when a breakpoint occurs. On the MC68010, MC68020, MC68030, and CPU32,

this function is provided via illegal instructions ($4848–$484F) that serve as breakpoint

instructions. See 5.5.2.5 Software Breakpoints for more information.

Unimplemented Instruction Emulation—When an attempt is made to execute an illegal

instruction, an illegal instruction exception occurs. Unimplemented instructions (F-line, A-

line) utilize separate exception vectors to permit efficient emulation of unimplemented

instructions in software. See 5.5.2.8 Illegal or Unimplemented Instructions for more

information.

5.6.1 CPU32 Integrated Development Support

In addition to standard MC68000 family capabilities, the CPU32 has features to support

advanced integrated system development. These features include background debug

mode, deterministic opcode tracking, hardware breakpoints, and internal visibility in a

single-chip environment.

Freescale Semiconductor, Inc.

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