MC68340 datasheet(204/441 Pages) FREESCALE

204 / 441 page

MOTOROLA

MC68340 USER’S MANUAL

5- 67

The CPU writes a unique value indicating the source of BDM transition into temporary

determine the source (see Table 5-20) by issuing a read system register command

(RSREG). ATEMP is used in most debugger commands for temporary storage—it is

imperative that the RSREG command be the first command issued after transition into

BDM.

Table 5-20. Polling the BDM Entry Source

Source

ATEMP 31–16

ATEMP 15–0

Double Bus Fault

SSW*

$FFFF

BGND Instruction

$0000

$0001

Hardware Breakpoint

$0000

*SSW is described in detail in 5.5.3 Fault Recovery.

A double bus fault during initial SP/PC fetch sequence is distinguished by a value of

$FFFFFFFF in the current instruction PC. At no other time will the processor write an odd

value into this register.

5.6.2.4 COMMAND EXECUTION. Figure 5-21 summarizes BDM command execution.

Commands consist of one 16-bit operation word and can include one or more 16-bit

extension words. Each incoming word is read as it is assembled by the serial interface.

The microcode routine corresponding to a command is executed as soon as the command

is complete. Result operands are loaded into the output shift register to be shifted out as

the next command is read. This process is repeated for each command until the CPU

returns to normal operating mode.

5.6.2.5 BDM REGISTERS. BDM processing uses three special-purpose registers to track

program context during development. A description of each register follows.

5.6.2.5.1 Fault Address Register (FAR). The FAR contains the address of the faulting

bus cycle immediately following a bus or address error. This address remains available

until overwritten by a subsequent bus cycle. Following a double bus fault, the FAR

contains the address of the last bus cycle. The address of the first fault (if one occurred) is

not visible to the user.

5.6.2.5.2 Return Program Counter (RPC). The RPC points to the location where fetching

will commence after transition from BDM to normal mode. This register should be

accessed to change the flow of a program under development. Changing the RPC to an

odd value will cause an address error when normal mode prefetching begins.

5.6.2.5.3 Current Instruction Program Counter (PCC). The PCC holds a pointer to the

first word of the last instruction executed prior to transition into BDM. Due to instruction

pipelining, the instruction pointed to may not be the instruction which caused the

transition. An example is a breakpoint on a released write. The bus cycle may overlap as

many as two subsequent instructions before stalling the instruction sequencer. A BKPT

asserted during this cycle will not be acknowledged until the end of the instruction

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68340 Datasheet(PDF) 204 Page - Freescale Semiconductor, Inc

MC68340 Datasheet(HTML) 204 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL