Electronic Components Datasheet Search
  English  ▼

X  

MC68340 Datasheet(PDF) 205 Page - Freescale Semiconductor, Inc

Part # MC68340
Description  Integrated Processor with DMA User?셲 Manual
PDF  441 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MC68340 Datasheet(HTML) 205 Page - Freescale Semiconductor, Inc

Back Button MC68340 Datasheet HTML 201Page - Freescale Semiconductor, Inc MC68340 Datasheet HTML 202Page - Freescale Semiconductor, Inc MC68340 Datasheet HTML 203Page - Freescale Semiconductor, Inc MC68340 Datasheet HTML 204Page - Freescale Semiconductor, Inc MC68340 Datasheet HTML 205Page - Freescale Semiconductor, Inc MC68340 Datasheet HTML 206Page - Freescale Semiconductor, Inc MC68340 Datasheet HTML 207Page - Freescale Semiconductor, Inc MC68340 Datasheet HTML 208Page - Freescale Semiconductor, Inc MC68340 Datasheet HTML 209Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 205 / 441 page
background image
5- 68
MC68340 USER’S MANUAL
MOTOROLA
executing at completion of the bus cycle. PCC will contain $00000001 if BDM is entered
via a double bus fault immediately out of reset.
..
YES
NO
CONTINUE
ENTER (BDM)
• ASSERT FREEZE SIGNAL
• WAIT FOR COMMAND
SEND INITIAL COMMAND
• LOAD COMMAND REGISTER
• ENABLE SHIFT CLOCK
• SHIFT OUT 17 BITS
• DISABLE SHIFT CLOCK
EXECUTE COMMAND
• LOAD: NOT READY/ RESPONSE
• PERFORM COMMAND
• STORE RESULTS
READ RESULTS/NEW COMMAND
• LOAD COMMAND REGISTER
• ENABLE SHIFT CLOCK
• SHIFT IN/OUT 17 BITS
• DISABLE SHIFT CLOCK
• READ RESULT REGISTER
IF RESULTS =
"NOT READY"
CPU32 ACTIVITY
DEVELOPMENT SYSTEM ACTIVITY
Figure 5-21. BDM Command Execution Flowchart
5.6.2.6 RETURNING FROM BDM. BDM is terminated when a resume execution (GO) or
call user code (CALL) command is received. Both GO and CALL flush the instruction
pipeline and prefetch instructions from the location pointed to by the RPC.
The return PC and the memory space referred to by the SR SUPV bit reflect any changes
made during BDM. FREEZE is negated prior to initiating the first prefetch. Upon negation
of FREEZE, the serial subsystem is disabled, and the signals revert to
IPIPE and IFETCH
functionality.
5.6.2.7 SERIAL INTERFACE. Communication with the CPU32 during BDM occurs via a
dedicated serial interface, which shares pins with other development features. The
BKPT
signal becomes the DSCLK; DSI is received on
IFETCH, and DSO is transmitted on
IPIPE.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com