Nexperia

74LVC2G240

Dual inverting buffer/line driver; 3-state

Table 9. Measurement points

Supply voltage

Input

Output

VCC

VM

VM

VX

VY

1.65 V to 1.95 V

0.5 × VCC

0.5 × VCC

VOL + 0.15 V

VOH - 0.15 V

2.3 V to 2.7 V

0.5 × VCC

0.5 × VCC

VOL + 0.15 V

VOH - 0.15 V

2.7 V

1.5 V

1.5 V

VOL + 0.3 V

VOH - 0.3 V

3.0 V to 3.6 V

1.5 V

1.5 V

VOL + 0.3 V

VOH - 0.3 V

4.5 V to 5.5 V

0.5 × VCC

0.5 × VCC

VOL + 0.3 V

VOH - 0.3 V

VEXT

VCC

VI

VO

mna616

DUT

CL

RT

RL

RL

G

Test data is given in Table 10.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig. 5. Test circuit for measuring switching times

Table 10. Test data

Supply voltage

Input

Load

VEXT

VCC

VI

CL

RL

tPLH, tPHL

tPZH, tPHZ

tPZL, tPLZ

1.65 V to 1.95 V

VCC

30 pF

1 kΩ

open

GND

2 × VCC

2.3 V to 2.7 V

VCC

30 pF

500 Ω

open

GND

2 × VCC

2.7 V

2.7 V

50 pF

500 Ω

open

GND

6 V

3.0 V to 3.6 V

2.7 V

50 pF

500 Ω

open

GND

6 V

4.5 V to 5.5 V

VCC

50 pF

500 Ω

open

GND

2 × VCC

74LVC2G240

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© Nexperia B.V. 2023. All rights reserved

Product data sheet

Rev. 12 — 1 June 2023

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