Nexperia

74LVC2G240

Dual inverting buffer/line driver; 3-state

6. Pinning information

6.1. Pinning

DP package

SOT505-2 (TSSOP8)

1OE

VCC

1A

2OE

2Y

1Y

GND

2A

aaa-036723

1

2

3

4

6

5

8

7

DC package

SOT765-1 (VSSOP8)

1OE

VCC

1A

2OE

2Y

1Y

GND

2A

aaa-036502

1

2

3

4

6

5

8

7

GT package

SOT833-1 (XSON8)

1Y

2OE

VCC

2A

2Y

1A

1OE

GND

aaa-036724

3

6

2

7

1

8

4

5

Transparent top view

1Y

2OE

VCC

2A

2Y

1A

1OE

GND

001aaf076

3

6

2

7

1

8

4

5

Transparent top view

GF package

SOT1089 (XSON8)

aaa-036725

GN package

SOT1116 (XSON8)

Transparent top view

1

8

1OE

VCC

2

7

1A

2OE

4

5

GND

2A

3

6

2Y

1Y

aaa-036726

GS package

SOT1203 (XSON8)

Transparent top view

1

8

1OE

VCC

2

7

1A

2OE

4

5

GND

2A

3

6

2Y

1Y

6.2. Pin description

Table 3. Pin description

Symbol

Pin

Description

1OE

1

output enable input 1OE (active LOW)

1A

2

data input

2Y

3

data output

GND

4

ground (0 V)

2A

5

data input

1Y

6

data output

2OE

7

output enable input 2OE (active LOW)

VCC

8

supply voltage

74LVC2G240

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© Nexperia B.V. 2023. All rights reserved

Product data sheet

Rev. 12 — 1 June 2023

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