Nexperia

74LVC32A

Quad 2-input OR gate

12. Abbreviations

Table 9. Abbreviations

Acronym

Description

CDM

Charged Device Model

CMOS

Complementary Metal-Oxide Semiconductor

DUT

Device Under Test

ESD

ElectroStatic Discharge

HBM

Human Body Model

MM

Machine Model

TTL

Transistor-Transistor Logic

13. Revision history

Table 10. Revision history

Document ID

Release date Data sheet status

Change notice Supersedes

74LVC32A v.8

20210827

Product data sheet

-

74LVC32A v.7

Modifications:

• Type number 74LVC32ADB (SOT337-1/SSOP14) removed.

74LVC32A v.7

20200527

Product data sheet

-

74LVC32A v.6

Modifications:

• Section 1 and Section 2 updated.

• Table 4: Derating values for Ptot total power dissipation updated.

74LVC32A v.6

20180912

Product data sheet

-

74LVC32A v.5

Modifications:

• The format of this data sheet has been redesigned to comply with the identity

guidelines of Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

• Package outline drawing SOT762-1 updated.

• Typo corrected in tpd value: 1.05 ns to 1.5 ns.

74LVC32A v.5

20111117

Product data sheet

-

74LVC32A v.4

Modifications:

• Legal pages updated.

• Table 6, ΔICC: condition VCC changed.

74LVC32A v.4

20111019

Product data sheet

-

74LVC32A v.3

74LVC32A v.3

20030716

Product specification

-

74LVC32A v.2

74LVC32A v.2

19970630

Product specification

-

74LVC32A v.1

74LVC32A v.1

19970630

Product specification

-

-

74LVC32A

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 8 — 27 August 2021

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