ADC08B3000 datasheet(22/32 Pages) NSC

22 / 32 page

1.0 Functional Description (Continued)

Offset Adjust

Addr: 2h (0010b)

W only (0x007F)

D15

D14

D13

D12

D11

D10

(MSB)

Offset Value

(LSB)

Sign

111111

Bits 15:8

Offset Value. The input offset of the ADC is

adjusted linearly and monotonically by the

value in this field. 00h provides a nominal

zero offset, while FFh provides a nominal 45

mV of offset. Thus, each code step provides

0.176 mV of offset.

POR State: 0000 0000 b

Bit 7

Sign bit. 0b gives positive offset, 1b gives

negative offset.

POR State: 0b

Bit 6:0

Must be set to 1b

Full-Scale Voltage Adjust

Addr: 3h (0011b)

W only (0x807F)

D15

D14

D13

D12

D11

D10

(MSB)

Adjust Value

(LSB)

111111

Bit 15:7

Full Scale Voltage Adjust Value. The input

full-scale voltage or gain of the ADC is

adjusted linearly and monotonically with a 9

bit data value. The adjustment range is

±20% of the nominal 700 mV

P-P differential

value.

0000 0000 0

560mV

P-P

1000 0000 0

Default Value

700mV

P-P

1111 1111 1

840mV

P-P

For best performance, it is recommended

that the value in this field be limited to the

range of 0110 0000 0b to 1110 0000 0b. i.e.,

limit the amount of adjustment to ±15%. The

remaining ±5% headroom allows for the

ADC’s own full scale variation. A gain

adjustment

does

not

require

ADC

re-calibration.

POR State: 1000 0000 0b (no adjustment)

Bits 6:0

Must be set to 1b

Extended Clock Phase Adjust Fine

Addr: Dh (1101b)

W only (0x3FFF)

D15

D14

D13

D12

D11

D10

(MSB)

FAM

(LSB)

111111

Bit 15:7

Fine Adjust Magnitude. With all bits set,

total adjust = 110ps of non-linear clock

adjust. The default setting is 000000000b

Bit 6:0

Must be set to 1b

Extended Clock Phase Adjust Coarse

Addr: Eh (1110b)

W only (0x07FF)

D15

D14

D13

D12

D11

D10

ENA

CAM

111111

Bit 15

Enable, default is 0b

Bit 14:11

Coarse Adjust Magnitude. Each LSB results

in approximately 70ps of clock adjust. The

default setting is 0000b

Bits 10:0

Must be set to 1b

FIFO Register

Addr: Fh (1111b)

W only (0xE7FF)

D15

D14

D13

D12

D11

D10

BZO

BZZ

ASW O2E

111111

Bit 14

BZZ: BSIZE0. Bit 14 in combination with

BSIZE1 (BIT 15) is used to select the buffer

size of the Capture Buffer. The Capture

Buffer is size adjustable and it cannot be split

between the two CMOS data output ports.

See Section 1.6 for a table which relates the

Capture Buffer size to BSIZE1 and BSIZE0

programming.

POR State: 1b

Bit 13

ASW: Auto-Stop Write. When ASW is logic 1,

the

Capture

Buffer

writes

will

stop

automatically when the Capture Buffer is full

of captured data and the FF flag is asserted.

this

bit

logic

the

device

will

continuously write data to the Capture Buffer

while overwriting previously captured data.

POR State: 1b

ADC08B3000 Datasheet(PDF) 22 Page - National Semiconductor (TI)

ADC08B3000 Datasheet(HTML) 22 Page - National Semiconductor (TI)

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