DP83848J datasheet(16/72 Pages) NSC

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2.2 AUTO-MDIX

When enabled, this function utilizes Auto-Negotiation to

determine the proper configuration for transmission and

reception of data and subsequently selects the appropri-

ate MDI pair for MDI/MDIX operation. The function uses a

random seed to control switching of the crossover cir-

cuitry. This implementation complies with the correspond-

ing

IEEE

802.3

Auto-Negotiation

and

Crossover

Specifications.

Auto-MDIX is enabled by default and can be configured

via strap or via PHYCR (0x19h) register, bits [15:14].

Neither Auto-Negotiation nor Auto-MDIX is required to be

enabled in forcing crossover of the MDI pairs. Forced

crossover can be achieved through the FORCE_MDIX bit,

bit 14 of PHYCR (0x19h) register.

Note: Auto-MDIX will not work in a forced mode of opera-

tion.

2.3 PHY ADDRESS

The 5 PHY address inputs pins are shared with the

RXD[3:0] pins and COL pin as shown below.

The DP83848J can be set to respond to any of 32 possi-

ble PHY addresses via strap pins. The information is

latched into the PHYCR register (address 19h, bits [4:0])

at device power-up and hardware reset. The PHY

Address pins are shared with the RXD and COL pins.

Each DP83848J or port sharing an MDIO bus in a system

must have a unique physical address.

The DP83848J supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). Strapping PHY Address

0 puts the part into Isolate Mode. It should also be noted

that selecting PHY Address 0 via an MDIO write to

PHYCR will not put the device in Isolate Mode. See

Section 2.3.1 for more information.

For further detail relating to the latch-in timing require-

ments of the PHY Address pins, as well as the other hard-

ware configuration pins, refer to the Reset summary in

Section 6.0.

Since the PHYAD[0] pin has weak internal pull-up resistor

and PHYAD[4:1] pins have weak internal pull-down resis-

tors, the default setting for the PHY address is 00001

(01h).

Refer to Figure 2 for an example of a PHYAD connection

to external components. In this example, the PHYAD

strapping results in address 00011 (03h).

2.3.1 MII Isolate Mode

The DP83848J can be put into MII Isolate mode by writing

to bit 10 of the BMCR register or by strapping in Physical

Address 0. It should be noted that selecting Physical

Address 0 via an MDIO write to PHYCR will not put the

device in the MII isolate mode.

When in the MII isolate mode, the DP83848J does not

respond to packet data present at TXD[3:0], TX_EN inputs

and presents a high impedance on the TX_CLK, RX_CLK,

RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When

in Isolate mode, the DP83848J will continue to respond to

all management transactions.

While in Isolate mode, the PMD output pair will not trans-

mit packet data but will continue to source 100BASE-TX

scrambled idles or 10BASE-T normal link pulses.

The DP83848J can Auto-Negotiate or parallel detect to a

specific technology depending on the receive signal at the

PMD input pair. A valid link can be established for the

receiver even when the DP83848J is in Isolate mode.

Table 2. PHY Address Mapping

Pin #

PHYAD Function

RXD Function

PHYAD0

COL

PHYAD1

RXD_0

PHYAD2

RXD_1

PHYAD3

RXD_2

PHYAD4

RXD_3

Figure 2. PHYAD Strapping Example

VCC

PHYAD0 = 1

PHYAD1 = 1

PHYAD2 = 0

PHYAD3 = 0

PHYAD4= 0

DP83848J Datasheet(PDF) 16 Page - National Semiconductor (TI)

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