AD1970 datasheet(12/20 Pages) AD

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AD1970

Rev. 0 | Page 12 of 20

CONTROL PORT

I2C PORT OVERVIEW

The AD1970 can be controlled using the I2C port. In general,

there are three parameters that can be controlled: the encoder

output level, the Phat Stereo image enhancement algorithm, and

the dialog enhancement algorithm. It is also possible to write

new data into the parameter RAM to alter the filter coefficients

used in the BTSC encoding process. Since this is a fairly

complex topic and is unnecessary for normal operation of the

chip, the details are not included in this data sheet; please

contact ADI sales if modifications to the BTSC filters are

required.

The I2C port uses a 2-wire interface consisting of SDA, the

bidirectional data line, and SCL, the clock.

The R/W bit is low for a write operation and high for a read

operation. The 10-bit address word is decoded into either a

location in the parameter RAM or one of the registers. The

number of data bytes varies according to the register or

memory being accessed. The detailed data format diagram for

continuous-mode operation is given in the section.

I2C ADDRESS DECODING

Table 16 shows the address decoding used in the I2C port. Four

different addresses are available to avoid conflicting addresses

on an I2C bus. The I2C address space encompasses a set a

registers and the parameter RAM. The parameter RAM is

loaded on power-up from an on-board boot ROM.

Table 16. I2C Address Settings

ADR1

ADR0

I2C Address

0x20

0x21

0x22

0x23

Table 17. I2C Port Address Decoding

Read/Write Word Length

Input Level Control

Write: 22 bits

Read: 22 bits

1 to 254

Parameter RAM

255

Output Level Control

256

Control Register 1

Write: 11 bits

Read: 6 bits

257

Control Register 2

Write: 22 bits

258

ADC Volume Control

259

Stereo Spreading Control

260

Dialog Enhancement Control

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