ADV7344 datasheet(77/88 Pages) AD

77 / 88 page

ADV7344

Rev. 0 | Page 77 of 88

622

623

624

625

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

DISPLAY

320

FIELD

HSYNC

Figure 105. SD Slave Mode 1, PAL

Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1)

In this mode, the ADV7344 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input

indicates a new frame, that is, vertical retrace. The ADV7344 automatically blanks all normally blank lines as per CCIR-624. Pixel data is

latched on the rising clock edge following the timing signal transitions. HSYNC and FIELD are output on the S_HSYNC and S_VSYNC

pins, respectively.

FIELD

PIXEL

DATA

HSYNC

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

Figure 106. SD Timing Mode 1, Odd/Even Field Transitions (Master/Slave)

Mode 2— Slave Option (Subaddress 0x8A = X X X X X 1 0 0)

In this mode, the ADV7344 accepts horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs

indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The ADV7344

automatically blanks all normally blank lines as per CCIR-624. HSYNC and VSYNC are input on the S_HSYNC and S_VSYNC pins,

respectively.

ADV7344 Datasheet(PDF) 77 Page - Analog Devices

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