AD5930 datasheet(19/28 Pages) AD

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AD5930

Rev. 0 | Page 19 of 28

SETTING UP THE FREQUENCY SWEEP

As stated previously in The Frequency Profile section, the

AD5930 requires certain registers to be programmed to enable a

frequency sweep. The following sections discuss these registers

in more detail.

Start Frequency (FSTART)

To start a frequency sweep, the user needs to tell the AD5930

what frequency to start sweeping from. This frequency is stored

in a 24-bit register called FSTART. If the user wishes to alter the

entire contents of the FSTART register, two consecutive writes

must be preformed, one to the LSBs and the other to the MSBs.

Note that for an entire write to this register, the Control Bit B24

(D11) should be set to 1 with the LSBs programmed first.

In some applications, the user does not need to alter all 24 bits

of the FSTART register. By setting the Control Bit B24 (D11) to 0,

the 24-bit register operates as two 12-bit registers, one

containing the 12 MSBs and the other containing the 12 LSBs.

This means that the 12 MSBs of the FSTART word can be altered

independently of the 12 LSBs, and vice versa. The addresses of

both the LSBs and the MSBs of this register is given in Table 8.

Table 8. FSTART Register Bits

D15

D14

D13

D12

D11 to D0

12 LSBs of FSTART <11…0>

12 MSBs of FSTART <23…12>

Frequency Increments (

∆f)

The value in the Δf register sets the increment frequency for the

sweep and is added incrementally to the current output frequency.

Note that the increment frequency can be positive or negative,

thereby giving an increasing or decreasing frequency sweep.

At the start of a sweep, the frequency contained in the FSTART

This is followed by (FSTART + Δf + Δf) and so on. Multiplying the

Δf value by the number of increments (NINCR), and adding it to

the start frequency (FSTART), gives the final frequency in the

sweep. Mathematically this final frequency/stop frequency is

represented by

FSTART + (NINCR × Δf).

The Δf register is a 23-bit register, and requires two 16-bit

writes to be programmed. Table 9 gives the addresses associated

with both the MSB and LSB registers of the Δf word.

Table 9. ∆f Register Bits

D15

D14

D13

D12

D11

D10 to D0

Sweep

Direction

12 LSBs of

∆f

<11…0>

N/A

11 MSBs of

Δf <22…12>

Positive

Δf

(FSTART +

Δf)

11 MSBs of

Δf <22…12>

Negative

∆f

(FSTART −

Δf)

Number of Increments (NINCR)

An end frequency, or a maximum/minimum frequency before

the sweep changes direction is not required on the AD5930.

Instead, this end frequency is calculated by multiplying the

frequency increment value (Δf) by the number of frequency

steps (NINCR), and adding it to/subtracting it from the start

frequency (FSTART), that is, FSTART + NINCR × Δ f. The NINCR register

is a 12-bit register, with the address shown in Table 10.

Table 10. NINCR Register Bits

D15

D14

D13

D12

D11 to D0

12 bits of NINCR <11…0>

The number of increments is programmed in binary fashion,

with 000000000010 representing the minimum number of

frequency increments (2 increments), and 111111111111

representing the maximum number of increments (4095).

Table 11. NINCR Data Bits

D11

Number of Increments

0000

0010

2 frequency increments. This is the

minimum number of frequency

increments.

0000

0011

3 frequency increments.

0000

0100

4 frequency increments.

…

1111

1110

4094 frequency increments.

1111

4095 frequency increments.

Increment Interval (tINT)

The increment interval dictates the duration of the DAC output

signal for each individual frequency of the frequency sweep.

The AD5930 offers the user two choices:

•

The duration is a multiple of cycles of the output frequency.

•

The duration is a multiple of MCLK periods.

This is selected by Bit D13 in the tINT register as shown in Table 12.

Table 12. tINT Register Bits

D15

D14

D13

D12

D11

D10 to D0

11 bits <10…0>

Fixed number of output

waveform cycles.

11 bits <10…0>

Fixed number of clock

periods.

Programming of this register is in binary form with the

minimum number being decimal 2. Note in Table 12 that 11

bits, Bit D10 to Bit D0, of the register are available to program

the time interval. As an example, if MCLK = 50 MHz, then each

clock period/base interval is (1/50 MHz) = 20 ns. If each

frequency needs to be output for 100 ns, then <00000000101>

or decimal 5 needs to be programmed to this register. Note that

the AD5930 can output each frequency for a maximum

duration of 211 −1 (or 2047) times the increment interval.

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