AD5932

Rev. 0 | Page 9 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TOP VIEW

(Not to Scale)

1

2

3

4

5

6

7

8

AD5932

16

15

14

13

12

11

10

9

AVDD

DVDD

CAP/2.5V

SYNCOUT

MCLK

DGND

COMP

AGND

STANDBY

FSYNC

CTRL

MSBOUT

INTERRUPT

SDATA

SCLK

VOUT

Figure 7. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

COMP

DAC Bias Pin. This pin is used for decoupling the DAC bias voltage to AVDD.

2

AVDD

Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling

capacitor should be connected between AVDD and AGND.

3

DVDD

Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling

capacitor should be connected between DVDD and DGND.

4

CAP/2.5V

Digital Circuitry. Operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board

regulator. The regulator requires a decoupling capacitor of typically 100 nF, which is connected from CAP/2.5V

to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5V can be shorted to DVDD.

5

DGND

Ground for All Digital Circuitry.

6

MCLK

Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK.

The output frequency accuracy and phase noise are determined by this clock.

7

SYNCOUT

Digital Output for Scan Status Information. User-selectable for end of scan (EOS) or frequency increments through

the control register (SYNCOP bit). This pin must be enabled by setting the SYNCOUTEN bit in the control register to 1.

8

MSBOUT

Digital Output. The inverted MSB of the DAC data is available at this pin. This output pin must be enabled by

setting the MSBOUTEN bit in the control register to 1.

9

INTERRUPT

Digital Input. This pin acts as an interrupt during a frequency scan. A low-to-high transition is sampled by the

internal MCLK, which resets internal state machines. This results in the DAC output going to midscale.

10

CTRL

Digital Input. Triple function pin for initialization, start, and external frequency increments. A low-to-high transition,

sampled by the internal MCLK, is used to initialize and start internal state machines, which then execute the pre-

programmed frequency scan sequence. When in auto-increment mode, a single pulse executes the entire scan

sequence. When in external increment mode, each frequency increment is triggered by low-to-high transitions.

11

SDATA

Serial Data Input. The 16-bit serial data-word is applied to this input with the register address first, followed by

the MSB to LSBs of the data.

12

SCLK

Serial Clock Input. Data is clocked into the AD5932 on each falling SCLK edge.

13

FSYNC

Active Low Control Input. This is the frame synchronization signal for the serial data. When FSYNC is taken low,

the internal logic is informed that a new word is being loaded into the device.

14

STANDBY

Active High Digital Input. When this pin is high, the internal MCLK is disabled, and the reference DAC and regulator

are powered down. For optimum power saving, it is recommended that the AD5932 be reset before it is put into

standby, as this results in a shutdown current of typically 20 μA.

15

AGND

Ground for All Analog Circuitry.

16

VOUT

Voltage Output. The analog outputs from the AD5932 are available here. An external resistive load is not required,

because the device has a 200 Ω resistor on board. A 20 pF capacitor to AGND is recommended to act as a low-pass

filter and to reduce clock feedthrough.