BSP110 datasheet(3/12 Pages) PHILIPS

3 / 12 page

April 1995

Philips Semiconductors

Product speciﬁcation

N-channel enhancement mode vertical

D-MOS transistor

BSP110

RATINGS

Limiting values in accordance with the Absolute Maximum System (IEC 134)

THERMAL RESISTANCE

Note

1. Device mounted on an epoxy printed-circuit board 40 mm

× 40 mm × 1.5 mm; mounting pad for the drain lead min.

6 cm2.

CHARACTERISTICS

Tj =25 °C unless otherwise speciﬁed

Drain-source voltage

VDS

max.

80 V

Drain-source voltage

(non-repetitive peak; tp ≤ 2 ms)

VDS(SM)

max.

100 V

Gate-source voltage (open drain)

± V

GSO

max.

20 V

Drain current (DC)

max.

325 mA

Drain current (peak)

IDM

max.

650 mA

Total power dissipation up to Tamb =25 °C (note 1)

Ptot

max.

1.5 W

Storage temperature range

Tstg

−65 to + 150 °C

Junction temperature

max.

150

°C

From junction to ambient (note 1)

Rth j-a

83.3 K/W

Drain-source breakdown voltage

ID =10 µA; VGS =0

V(BR) DSS

min.

80 V

Drain-source leakage current

VDS = 60 V; VGS =0

IDSS

max.

1.0

µA

Gate-source leakage current

VGS = 20 V; VDS =0

IGSS

max.

100 nA

Gate threshold voltage

min.

max.

0.8

2.8

ID = 1 mA; VDS =VGS

IGS(th)

Drain-source ON-resistance (see Fig.4)

typ.

max.

Ω

ID = 150 mA; VGS =5V

RDS(on)

ID = 200 mA; VGS =10V

RDS(on)

typ.

max.

4.5

Ω

Transfer admittance

min.

typ.

150

ID = 200 mA; VDS =5V

| Yfs|

Input capacitance at f = 1 MHz;

typ.

max.

VDS = 10 V; VGS =0

Ciss

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