AD7367 datasheet(15/16 Pages) AD

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Preliminary Technical Data

AD7367

Rev. PrD | Page 15 of 16

SERIAL INTERFACE

Figure 9 shows the detailed timing diagram for serial inter-

facing to the AD7367. On the falling edge of CONVST the

AD7367 will simultaneously convert the selected channels.

These conversions are performed using the on-chip oscillator.

After the falling edge of CONVST the BUSY signal goes high,

indicating the conversion has started. It returns low once the

conversion has been completed. The data can now be read from

the

DOUT pins.

CS and SCLK signals are required to transfer data from the

AD7367. The AD7367 has two output pins corresponding to

each ADC. Data can be read from the AD7367 using both

DOUTA & DOUTB, alternatively a single output pin of your

choice can be used. The SCLK input signal provides the

clock source for the serial interface. The CS goes low to

access data from the AD7367. The falling edge of CS takes

the bus out of three-state and clocks out the MSB of the

conversion result. The data stream consists of 14 bits of data

MSB first. The first bit of the conversion result is valid on the

first SCLK falling edge after the CS falling edge. The

subsequent 13 bits of data are clocked out on the falling edge

of the SCLK signal. A minimum of 14 Clock pulses must be

provided to AD7367 to access each conversion result. Figure

shows how a 14 SCLK read is used to access the conversion

results.

On the rising edge of CS, the conversion will be terminated

and DOUTA and DOUTB go back into three-state. If CS is not

brought high, but is instead held low for a further 14 SCLK

cycles on either DOUTA or DOUTB, the data from the other

ADC follows on the DOUT pin. This is illustrated in Figure 10

where the case for DOUTA is shown. In this case, the DOUT

line in use goes back into three-state on the rising edge of CS

If the falling edge of SCLK coincides with the falling edge of

CS, then the falling edge of SCLK is not acknowledged by

the AD7367, and the next falling edge of the SCLK will be

the first registered after the falling edges of the CS.

The CS pin can be brought low before the BUSY signal goes

low indicating the end of a conversion. This feature can be

utilized to ensure that the MSB is valid on the falling edge of

BUSY by bring CS low a minimum of t4 nanoseconds before the

BUSY signal goes low. The dotted CS

line in Table 7 illustrates

this.

SCLK

DOUTA

DOUTB

3-STATE

DB13

DB12

DB2

DB0

DB1

DB11

DB10

Figure 9. Serial Interface Timing diagram

SCLK

DOUTA

THREE-

STATE

THREE-

STATE

DB13B

t10

DB13A

DB12A DB11A

DB1A

DB0A

DB1B

DB0B

DB12B

Figure 10. Reading Data from Both ADC’s on ONE DOUT Line with 28 SCLK’s

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