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74LVC1G10GM Datasheet(PDF) 2 Page - Nexperia B.V. All rights reserved |
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74LVC1G10GM Datasheet(HTML) 2 Page - Nexperia B.V. All rights reserved |
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2 / 15 page ![]() Nexperia 74LVC1G10 Single 3-input NAND gate 3. Ordering information Table 1. Ordering information Package Type number Temperature range Name Description Version 74LVC1G10GW -40 °C to +125 °C TSSOP6 plastic thin shrink small outline package; 6 leads; body width 1.25 mm SOT363-2 74LVC1G10GV -40 °C to +125 °C SC-74; TSOP6 plastic surface-mounted package; 6 leads SOT457 74LVC1G10GM -40 °C to +125 °C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1 × 1.45 × 0.5 mm SOT886 74LVC1G10GN -40 °C to +125 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 0.9 × 1.0 × 0.35 mm SOT1115 74LVC1G10GS -40 °C to +125 °C XSON6 extremely thin small outline package; no leads; 6 terminals; body 1.0 × 1.0 × 0.35 mm SOT1202 4. Marking Table 2. Marking Type number Marking code [1] 74LVC1G10GW YM 74LVC1G10GV YM 74LVC1G10GM YM 74LVC1G10GN YM 74LVC1G10GS YM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 001aag686 3 B 6 C 1 A Y 4 Fig. 1. Logic symbol 001aag687 & 1 3 4 6 Fig. 2. IEC logic symbol 001aag688 B Y A C Fig. 3. Logic diagram 74LVC1G10 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 7 — 2 February 2022 2 / 15 |
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