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74AHC594DB Datasheet(PDF) 17 Page - NXP Semiconductors |
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74AHC594DB Datasheet(HTML) 17 Page - NXP Semiconductors |
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17 / 29 page ![]() 74AHC_AHCT594_1 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 01 — 4 July 2006 17 of 29 Philips Semiconductors 74AHC594; 74AHCT594 8-bit shift register with output register tsu set-up time DS to SHCP CL = 50 pF; see Figure 11 3.0 - - ns set-up time SHR to STCP CL = 50 pF; see Figure 12 5.0 - - ns set-up time SHCP to STCP CL = 50 pF; see Figure 10 5.0 - - ns th hold time DS to SHCP see Figure 11 2.0 - - ns trec recovery time SHR to SHCP CL = 50 pF; see Figure 13 2.9 - - ns recovery time STR to STCP CL = 50 pF; see Figure 14 3.4 - - ns fmax maximum frequency SHCP or STCP CL = 50 pF; see Figure 9 and Figure 10 90 160 - MHz CPD power dissipation capacitance VI = GND to VCC; VCC =5V; CL = 50 pF; fi = 1 MHz [2] -55 - pF Tamb = −40 °C to +85 °C tPLH LOW-to-HIGH propagation delay SHCP to Q7S see Figure 9 CL = 15 pF 1.7 - 7.2 ns CL = 50 pF 2.2 - 9.1 ns tPHL HIGH-to-LOW propagation delay SHCP to Q7S see Figure 9 CL = 15 pF 1.8 - 7.6 ns CL = 50 pF 2.4 - 10.1 ns tPLH LOW-to-HIGH propagation delay STCP to Qn see Figure 10 CL = 15 pF 1.8 - 6.5 ns CL = 50 pF 2.6 - 8.8 ns tPHL HIGH-to-LOW propagation delay STCP to Qn see Figure 10 CL = 15 pF 1.9 - 6.9 ns CL = 50 pF 2.6 - 9.7 ns tPHL HIGH-to-LOW propagation delay SHR to Q7S see Figure 13 CL = 15 pF 2.4 - 8.0 ns CL = 50 pF 2.7 - 10.1 ns HIGH-to-LOW propagation delay STR to Qn see Figure 14 CL = 15 pF 2.3 - 8.4 ns CL = 50 pF 3.1 - 10.7 ns tW pulse width HIGH or LOW SHCP and STCP CL = 50 pF; see Figure 9 and Figure 10 6.0 - - ns pulse width HIGH or LOW SHR and STR CL = 50 pF; see Figure 13 and Figure 14 5.5 - - ns Table 9. Dynamic characteristics type 74AHCT594 …continued GND = 0 V; tr = tf ≤ 3.0 ns; VCC = 4.5 V to 5.5 V; see Figure 15 Symbol Parameter Test conditions Min Typ Max Unit |
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