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Product data sheet

Rev. 01 — 2 June 2005

6 of 19

Philips Semiconductors

GTL2007

13-bit GTL to LVTTL translator with power good control

[1]

The enable on 7BO1/7BO2 includes a delay that prevents the transient condition where 5BI/6BI go from

LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns from causing a low glitch on the

7BO1/7BO2 outputs.

[2]

Open-drain input/output terminal is driven to logic LOW state by other driver.

[1]

Open-drain input/output terminal is driven to logic LOW state by other driver.

Table 7:

SMI signals

H = HIGH voltage level; L = LOW voltage level.

Input

Input

Output

10AI1/10AI2

9BI

10BO1/10BO2

LLL

LH

L

HL

L

HHH

Table 8:

PROCHOT signals

H = HIGH voltage level; L = LOW voltage level.

Input

Input/output

Output

5BI/6BI

5A/6A (open-drain)

7BO1/7BO2

LLH [1]

HL [2]

L

HHH

Table 9:

NMI signals

H = HIGH voltage level; L = LOW voltage level.

Input

Input/output

Output

11BI

11A (open-drain)

11BO

LH

L

LL [1]

H

HL

H