LPC2378 datasheet(19/54 Pages) PHILIPS

19 / 54 page

LPC2378_1

Preliminary data sheet

Rev. 01 — 6 December 2006

19 of 54

NXP Semiconductors

LPC2378

Fast communication chip

• Static memory features include:

– Asynchronous page mode read

– Programmable Wait States (WST)

– Bus turnaround delay

– Output enable and write enable delays

– Extended wait

7.8 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2378

peripherals to have DMA support.

The GPDMA enables peripheral-to-memory, memory-to-peripheral,

peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream

provides unidirectional serial DMA transfers for a single source and destination. For

example, a bidirectional port requires one stream for transmit and one for receive. The

source and destination areas can each be either a memory region or a peripheral, and

can be accessed through the AHB master.

7.8.1 Features

• Two DMA channels. Each channel can support a unidirectional transfer.

• The GPDMA can transfer data between the 8 kB SRAM and peripherals such as the

SD/MMC, two SSP, and I2S interfaces.

• Single DMA and burst DMA request signals. Each peripheral connected to the

GPDMA can assert either a burst DMA request or a single DMA request. The DMA

burst size is set by programming the GPDMA.

• Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and

peripheral-to-peripheral transfers.

• Scatter or gather DMA is supported through the use of linked lists. This means that

the source and destination areas do not have to occupy contiguous areas of memory.

• Hardware DMA channel priority. Each DMA channel has a speciﬁc hardware priority.

DMA channel 0 has the highest priority and channel 1 has the lowest priority. If

requests from two channels become active at the same time, the channel with the

highest priority is serviced ﬁrst.

• AHB slave DMA programming interface. The GPDMA is programmed by writing to the

DMA control registers over the AHB slave interface.

• One AHB bus master for transferring data. This interface transfers data when a DMA

request goes active.

• 32-bit AHB master bus width.

• Incrementing or non-incrementing addressing for source and destination.

• Programmable DMA burst size. The DMA burst size can be programmed to more

efﬁciently transfer data. Usually the burst size is set to half the size of the FIFO in the

peripheral.

• Internal four-word FIFO per channel.

• Supports 8-bit, 16-bit, and 32-bit wide transactions.

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