TSB41AB3IPFP datasheet(33/52 Pages) TI

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TSB41AB3

IEEE 1394a2000 THREEPORT CABLE TRANSCEIVER/ARBITER

SLLS418I − JUNE 2000 − REVISED DECEMBER 2004

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

LLC service request

To request access to the bus, to read or write a PHY register, or to control arbitration acceleration, the LLC sends

a serial bit stream on the LREQ terminal as shown in Figure 16.

Each cell represents one clock sample time, and n is the number of bits in the request stream.

LR1

LR2

LR3

LR (n-2)

LR0

LR (n-1)

Figure 16. LREQ Request Stream

The length of the stream varies depending on the type of request as shown in Table 12.

Table 12. Request Stream Bit Length

REQUEST TYPE

NUMBER OF BITS

Bus request

7 or 8

Read register request

Write register request

Acceleration control request

Regardless of the type of request, a start-bit of 1 is required at the beginning of the stream, and a stop-bit of

0 is required at the end of the stream. The second through fourth bits of the request stream indicate the type

of the request. In the descriptions below, bit 0 is the most significant and is transmitted first in the request bit

stream. The LREQ terminal is normally low.

Encoding for the request type is shown in Table 13.

Table 13. Request Type Encoding

LR1-LR3

NAME

DESCRIPTION

000

ImmReq

Immediate bus request. Upon detection of idle, the PHY takes control of the bus immediately without arbitration.

001

IsoReq

Isochronous bus request. Upon detection of idle, the PHY arbitrates for the bus without waiting for a subaction gap.

010

PriReq

Priority bus request. The PHY arbitrates for the bus after a subaction gap, ignores the fair protocol.

011

FairReq

Fair bus request. The PHY arbitrates for the bus after a subaction gap, follows the fair protocol.

100

RdReg

The PHY returns the specified register contents through a status transfer.

101

WrReg

Write to the specified register

110

AccelCtl

Enable or disable asynchronous arbitration acceleration

111

Reserved

For a bus request the length of the LREQ bit stream is 7 or 8 bits as shown in Table 14.

Table 14. Bus Request

BIT(s)

NAME

DESCRIPTION

Start bit

Indicates the beginning of the transfer (always 1).

1-3

Request type

Indicates the type of bus request. See Table 13.

4-6

Request speed

Indicates the speed at which the PHY sends the data for this request. See Table 15 for the encoding of this field.

Stop bit

Indicates the end of the transfer (always 0). If bit 6 is 0, this bit may be omitted.

TSB41AB3IPFP Datasheet(PDF) 33 Page - Texas Instruments

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