AD9246 datasheet(21/44 Pages) AD

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AD9246

Rev. A | Page 21 of 44

290

215

CLOCK FREQUENCY (MSPS)

150

120

IDRVDD

IAVDD

TOTAL POWER

275

260

245

230

Figure 54. AD9246-80 Power and Current vs. Clock Frequency fIN = 30 MHz

Power-Down Mode

By asserting the PDWN pin high, the AD9246 is placed in

power-down mode. In this state, the ADC typically dissipates

1.8 mW. During power-down, the output drivers are placed in

a high impedance state. Reasserting the PDWN pin low returns

the AD9246 to its normal operational mode. This pin is both

1.8 V and 3.3 V tolerant.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. The decoupling capacitors on REFT and REFB are

discharged when entering power-down mode and then must be

recharged when returning to normal operation. As a result, the

wake-up time is related to the time spent in power-down mode;

and shorter power-down cycles result in proportionally shorter

wake-up times. With the recommended 0.1 μF decoupling

capacitors on REFT and REFB, it takes approximately 0.25 ms

to fully discharge the reference buffer decoupling capacitors and

0.35 ms to restore full operation.

Standby Mode

When using the SPI port interface, the user can place the ADC

in power-down mode or standby mode. Standby mode allows the

user to keep the internal reference circuitry powered when

faster wake-up times are required (see the Memory Map section).

DIGITAL OUTPUTS

The AD9246 output drivers can be configured to interface with

1.8 V to 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic. The output drivers are sized to

provide sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fan-outs may require external buffers or latches.

The output data format can be selected for either offset binary

or twos complement by setting the SCLK/DFS pin when operat-

ing in the external pin mode (see Table 10).

As detailed in the Interfacing to High Speed ADCs via SPI User

Manual, the data format can be selected for either offset binary,

twos complement, or Gray code when using the SPI control.

Out-of-Range (OR) Condition

An out-of-range condition exists when the analog input voltage

is beyond the input range of the ADC. OR is a digital output

that is updated along with the data output corresponding to the

particular sampled input voltage. Thus, OR has the same pipeline

latency as the digital data.

OR DATA OUTPUTS

+FS – 1 LSB

+FS – 1/2 LSB

+FS

–FS

–FS + 1/2 LSB

–FS – 1/2 LSB

1111

1110

0000

0001

0000

Figure 55. OR Relation to Input Voltage and Output Data

OR is low when the analog input voltage is within the analog

input range and high when the analog input voltage exceeds the

input range, as shown in Figure 55. OR remains high until the

analog input returns to within the input range, and another conver-

sion is completed. By logically AND’ing the OR bit with the MSB

and its complement, overrange high or underrange low conditions

can be detected. Table 11 is a truth table for the overrange/

underrange circuit in Figure 56, which uses NAND gates.

MSB

OVER = 1

UNDER = 1

Figure 56. Overrange/Underrange Logic

Table 11. Overrange/Underrange Truth Table

MSB

Analog Input Is:

Within range

Underrange

Overrange

Digital Output Enable Function (OEB)

The AD9246 has three-state ability. If the OEB pin is low, the

output data drivers are enabled. If the OEB pin is high, the

output data drivers are placed in a high impedance state. This is

not intended for rapid access to the data bus. Note that OEB is

referenced to the digital supplies (DRVDD) and should not

exceed that supply voltage.

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