2–210

SCF5740/2/4

Figure 11. Display Interface to Siemens/Intel 8031 Microprocessor (using one bit of parallel port as serial port)

Figure 12. Display Interface with Motoroal 68HC05C4 Microprocessor (using SPI Port)

Figure 13. Cascading Multiple Displays

Multiple displays can be cascaded using the CLK SEL and CLK I/O pins (Figure 13). The display designated as the Master-

Clock source should have its CLK SEL pin tied high and the slaves should have their CLK SEL pins tied low. All CLK I/O pins

should be tied together. One display CLK I/O can drive 15 slave CLK I/Os. Use RST to synchronize all display counters.

U1

8031

1

9

20

RST

P1.0

18

19

XTAL2

XTAL1

40 P3.0

P3.1

P3.6

P0.0

10

11

16

39

10

21

8

22

µF

TAN

.01

µF

GND

DATA

CLKSEL

CLK I/O

SDCLK

LD

RST

GND

ID

+

15

13

19

2

14

U1

68HC05C4

1

9

20

RST

PA2

38

39

OSC1

OSC2

40

PA0

PA1

SCLK

MOSI

11

10

33

32

10

21

8

22

µF

TAN

.01

µF

GND

DATA

CS

CLK I/O

SDCLK

LD

RST

GND

ID

+

15

13

19

2

14

RST

CLK I/O

CLK SEL

DATA

SDCLK

LOAD

14 more displays

in between

RST

CLK I/O

CLK SEL

DATA SDCLK

LOAD

Chip

Address

Decoder

0

15

Address Decode 1–14

RST

DATA

SDCLK

A0

A1

A2

A3

LD

Intelligent Display

Intelligent Display

CE