Nexperia

74HC237

3-to-8 line decoder, demultiplexer with address latches

tsu

th

LE input

VM

VM

001aab875

th

tsu

tW

An input

transparant

transparant

latched

latched

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 9. The data input (An) to latch enable input (LE) set-up times, latch enable input (LE) to data input (An) hold

times and latch enable input (LE) pulse width

Table 8. Measurement points

Input

Output

VM

VM

0.5VCC

0.5VCC

001aah768

tW

tW

tr

tr

tf

VM

VI

negative

pulse

GND

VI

positive

pulse

GND

10 %

90 %

90 %

10 %

VM

VM

VM

tf

VCC

DUT

RT

VI

VO

CL

G

Test data is given in Table 9.

Definitions test circuit:

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

CL = Load capacitance including jig and probe capacitance.

Fig. 10. Test circuit for measuring switching times

Table 9. Test data

Input

Load

VI

tr, tf

CL

Test

VCC

6.0 ns

15 pF, 50 pF

tPLH, tPHL

74HC237

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 8 — 26 October 2021

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