TPCF8301 datasheet(1/5 Pages) TOSHIBA

Part #	TPCF8301

Description	FIELD EFFECT TRANSISTOR SILICON P CHANNEL MOS TYPE(U竊뛏OS??

PDF	5 Pages

Scroll/Zoom	100%

Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

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ＴＯＳＨＩＢＡ

TPCF8301

TOSHIBA FIELD EFFECT TRANSISTOR SILICON P CHANNEL MOS TYPE(U−MOSⅢ)

ＴＰＣＦ８３０１

NOTE

BOOK

PC

APPLICATIONS

PORTABLE

EQUIPMENTS

APPLICATIONS

UNIT:mm

・Low Drain - Source ON Resistance：ＲＤＳ(ＯＮ)＝72ｍΩ(Typ.)

・High Forward Transfer Admittance：￨Ｙｆｓ￨＝6 S(Typ.)

・Low Leakage Current：ＩＤＳＳ＝-10μＡ(Max.) (ＶＤＳ＝-20Ｖ)

・Enhancement - Mode：Ｖｔｈ＝-0.5 ∼ -1.2Ｖ(ＶＤＳ＝-10Ｖ,ＩＤ＝-200µＡ)

Maximum Ratings (Ta=25℃)

Characteristics

Symbol

Rating

Unit

Drain-source voltage

ＶＤＳＳ

-20

Ｖ

Drain-gate voltage(RGS=20kΩ)

ＶＤＧＲ

-20

Ｖ

Gate-source voltage

ＶＧＳＳ

±8

Ｖ

DC

(Note 1)

ＩＤ

-2.7

Drain current

Pulse

(Note 1)

ＩＤＲ

-10.8

Ａ

Single-device operation

(Note 3a)

ＰＤ(1)

1.35

Drain power

dissipation

(t=5s)(Note 2a) Single-device value at

dual operation (Note 3b)

ＰＤ(2)

1.12

Single-device operation

(Note 3a)

ＰＤ(1)

0.53

Drain power

dissipation

(t=5s)(Note 2b) Single-device value at

dual operation (Note 3b)

ＰＤ(2)

0.33

Ｗ

Single pulse avalanche energy (Note 4)

ＥＡＳ

1.2

ｍＪ

Avalanche current

ＩＡＲ

-1.35

Ａ

Repetitive avalanche energy

Single-device

value at dual operation

(Note 2a,3b,5)

ＥＡＲ

0.11

ｍＪ

Channel temperature

Ｔｃｈ

150

℃

Storage temperature range

Ｔｓｔｇ -55∼150

℃

THERMAL CHARACTERISTICS

Characteristics

Symbol

Max

Unit

Single-device

operation (Note 3a)

Rth(ch-a)(1)

92.6

Thermal resistance,

channel to ambient

(t=5s)

(Note 2a)

Single-device value at

dual operation (Note 3b)

Rth(ch-a)(2)

111.6

℃/Ｗ

Single-device

operation (Note 3a)

Rth(ch-a)(1)

235.8

Thermal resistance,

channel to ambient

(t=5s)

(Note 2b)

Single-device value at

dual operation (Note 3b)

Rth(ch-a)(2)

378.8

℃/Ｗ

Note1, Note2, Note3, Note4, Note5 Please see next page.

THIS TRANSISTOR IS AN ELECTROSTATIC SENSITIVE DEVICE.

1

2

3

4

5

6

8

7

Ｔｅ

Ｔｅｎｔａｔｉｖｅ

ｎｔａｔｉｖｅ

Circuit

Configuration

ＪＥＤＥＣ

―

ＪＥＩＴＡ

―

TOSHIBA

―

1. Drain

2. Drain

3. Gat

4. Source

5. Drain

6. Drain

0.05

2.9

±0.2

0.3

±0.1

0.95

0.25 -0.15

+0.25

1

4

3

6

0.95

1：DRAIN

5：SOURCE

2：DRAIN

6：DRAIN

3：DRAIN

7：DRAIN

4：GATE

8：DRAIN

2.9±0.1

0.3 +0.1／-0.05

0.65

0.8±0.05

1111

4444

5555

8888

1：SOURCE1 5：DRAIN 2

2：GATE 1

6：DRAIN2

3：SOURCE2 7：DRAIN1

4：GATE2

8：DRAIN1

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