Nexperia

74HC10; 74HCT10

Triple 3-input NAND gate

5. Pinning information

5.1. Pinning

74HC10

74HCT10

1A

VCC

1B

1C

2A

1Y

2B

3C

2C

3B

2Y

3A

GND

3Y

aaa-024297

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 4. Pin configuration SOT108-1 (SO14)

74HC10

74HCT10

1A

VCC

1B

1C

2A

1Y

2B

3C

2C

3B

2Y

3A

GND

3Y

aaa-024298

1

2

3

4

5

6

7

8

10

9

12

11

14

13

Fig. 5. Pin configuration SOT402-1 (TSSOP14)

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1A, 2A, 3A

1, 3, 9

data input

1B, 2B, 3B

2, 4, 10

data input

GND

7

ground (0 V)

1C, 2C, 3C

13, 5, 11

data input

1Y, 2Y, 3Y

12, 6, 8

data output

VCC

14

supply voltage

6. Functional description

Table 3. Function selection

H = HIGH voltage level; L = LOW voltage level; X = don’t care

Input

Output

nA

nB

nC

nY

L

X

X

H

X

L

X

H

X

X

L

H

H

H

H

L

74HC_HCT10

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 4 — 8 January 2021

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