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MT8889CS Datasheet(PDF) 2 Page - Zarlink Semiconductor Inc

Part # MT8889CS
Description  Integrated DTMF Transceiver with Adaptive Micro Interface
PDF  31 Pages
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT8889CS Datasheet(HTML) 2 Page - Zarlink Semiconductor Inc

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MT8889C
2
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
20
24
1
1
IN+
Non-inverting op-amp input.
2
2
IN-
Inverting op-amp input.
33
GS
Gain Select. Gives access to output of front end differential amplifier for connection of
feedback resistor.
44
VRef
Reference Voltage output (VDD/2).
55
VSS
Ground (0V).
6
6
OSC1 DTMF clock/oscillator input. Connect a 4.7M
Ω resistor to VSS if crystal oscillator is
used.
7
7
OSC2 Oscillator output. A 3.579545 MHz crystal connected between OSC1 and OSC2
completes the internal oscillator circuit. Leave open circuit when OSC1 is driven externally.
8
10
TONE Output from internal DTMF transmitter.
9
11
R/W
(WR)
(Motorola) Read/Write or (Intel) Write microprocessor input. TTL compatible.
10
12
CS
Chip Select input. This signal must be qualified externally by either address strobe (AS),
valid memory address (VMA) or address latch enable (ALE) signal, see Figure 12.
11
13
RS0
Register Select input. Refer to Table 3 for bit interpretation. TTL compatible.
12
14
DS
(RD)
(Motorola) Data Strobe or (Intel) Read microprocessor input. Activity on this input is only
required when the device is being accessed. TTL compatible.
13
15
IRQ/
CP
Interrupt Request/Call Progress (open drain) output. In interrupt mode, this output goes
low when a valid DTMF tone burst has been transmitted or received. In call progress mode,
this pin will output a rectangular signal representative of the input signal applied at the input
op-amp. The input signal must be within the bandwidth limits of the call progress filter, see
Figure 8.
14-
17
18-21
D0-D3 Microprocessor data bus. High impedance when CS = 1 or DS =0 (Motorola) or RD = 1
(Intel). TTL compatible.
18
22
ESt
Early Steering output. Presents a logic high once the digital algorithm has detected a valid
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return
to a logic low.
19
23
St/GT Steering Input/Guard Time output (bidirectional). A voltage greater than VTSt detected at
St causes the device to register the detected tone pair and update the output latch. A
voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to
reset the external steering time-constant; its state is a function of ESt and the voltage on St.
20
24
VDD
Positive power supply (5V typical).
8, 9,
16,17
NC
No Connection.
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
TONE
R/W/WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
IRQ/CP
DS/RD
RS0
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
IN+
IN-
GS
VRef
VSS
OSC1
OSC2
NC
TONE
R/W/WR
CS
VDD
St/GT
ESt
D3
D2
D1
D0
NC
NC
IRQ/CP
DS/RD
RS0
24 PIN SSOP
20 PIN PLASTIC DIP/SOIC



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