Nexperia

74HC160

Presettable synchronous BCD decade counter; asynchronous reset

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

MR

1

asynchronous master reset (active LOW)

CP

2

clock input (LOW-to-HIGH, edge triggered)

D0, D1, D2, D3

3, 4, 5, 6

data input

CEP

7

count enable input

GND

8

ground (0 V)

PE

9

parallel enable input (active LOW)

CET

10

count enable carry input

Q0, Q1, Q2, Q3

14, 13, 12, 11

flip-flop output

TC

15

terminal count output

VCC

16

supply voltage

6. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition;

h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;

I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;

qn = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition.

Inputs

Outputs

Operating mode

MR

CP

CEP

CET

PE

Dn

Qn

TC

Reset (clear)

L

X

X

X

X

X

L

L

H

↑

X

X

I

I

L

L

Parallel load

H

↑

X

X

I

h

H

[1]

Count

H

↑

h

h

h

X

count

[1]

H

X

I

X

h

X

qn

[1]

Hold (do nothing)

H

X

X

I

h

X

qn

L

[1] The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH);

aaa-024742

0

15

14

13

5

6

7

12

1

2

3

4

11

10

9

8

Fig. 6. State diagram

74HC160

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© Nexperia B.V. 2019. All rights reserved

Product data sheet

Rev. 4 — 27 March 2019

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