Data Sheet G13690EJ3V0DS00

12

µµµµ PC1933

2.5

PWM Comparator

The output ON duty is controlled according to the outputs of the error amplifier.

A triangular waveform is input to the inverted pin, and the error amplifier output and Dead Time Control pin voltage (fixed

internally) are input to the non-inverted pins of the PWM comparator. Therefore, the output transistor ON period is the

period when the triangular waveform is lower than the error amplifier output and Dead Time Control pin voltage (fixed

internally) (refer to Timing Chart).

2.6

Timer Latch-Method Short Circuit Protection Circuit

When the output of the converter drops, the non-inverted input pin (1 pin) voltage of the error amplifier drops, and the

FB output of the error amplifier of the output goes high. If the FB output exceeds the timer latch input detection voltage

(VTH = 1.92 V), then the output of the SCP comparator goes low, and Q1 goes off.

When Q1 turns OFF, the constant-current supply charges CDLY via the DLY pin. The DLY pin is internally connected to a

flip-flop. When the DLY pin voltage reaches the UV detection voltage (VUV = 0.7 V (TYP.)), the output Q of the flip-flop goes

low, and the output stage is latched to OFF (refer to Figure 2-1 Block Diagram).

Make the power supply voltage briefly less than the reset voltage (VCCR, 1.0 V TYP.) to reset the latch circuit when the

short-circuit protection circuit has operated.

2.7

Output Circuit

The output circuit has an N-channel open-drain output providing an output withstand voltage of 30 V (absolute maximum

rating), and an output current of 21 mA (absolute maximum rating).