Nexperia

74ALVT16821

20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state

74ALVT16821

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Product data sheet

Rev. 4 — 22 January 2018

10 / 16

001aaa257

GND

GND

th

tsu

th

tsu

VM

VM

VM

VI

VOH

VOL

VI

nQn output

nCP input

nDn input

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 6. Set-up times and hold times data input (nDn) to clock input (nCP)

001aal795

tPLZ

tPHZ

outputs

disabled

outputs

enabled

VY

VX

outputs

enabled

nQn output

LOW-to-OFF

OFF-to-LOW

nQn output

HIGH-to-OFF

OFF-to-HIGH

nOE input

VI

VOL

VOH

VCC

VM

VM

GND

GND

tPZL

tPZH

VM

VM

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Figure 7. OFF-state to HIGH and LOW propagation delays and LOW and HIGH to OFF-state propagation delays

Table 8. Measurement points

Input

Output

VCC

VM

VM

VX

VY

VCC ≤ 2.7 V

0.5 x VCC

0.5 x VCC

VOL + 0.15 V

VOH - 0.15 V

VCC ≥ 3.0 V

1.5 V

1.5 V

VOL + 0.3 V

VOH - 0.3 V