DS1610 datasheet(3/10 Pages) DALLAS

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DS1610

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st through 24th read cycle as defined by A

W through AZ and shown in Table 2. A logical 1 in a bit

location sets that partition to write protect. A logical 0 in a bit location disables write protection. For

example, if during the pattern match sequence bit 22 on address pin AX were a 1, this would cause the

partition register location for partition 5 to be set to a 1. This in turn would cause the DS1610 to inhibit

WEO

from going low as WEI goes low whenever AZAYAXAW=0101. Note that while setting the partition

cycles is to set the partition switch and not for the purpose of accessing data from RAM. Also note that on

initial battery attach the partition register can power-up in any state.

PATTERN MATCH TO WRITE PARTITION REGISTER Table 1

12345678910

1011110011

1111100111

1111001110

1100011100

PARTITION REGISTER MAPPING Table 2

Address

Bit number in pattern

Match sequence

Partition Number

Address State Affected

(AZ AY AX AW)

BIT 21

PARTITION 0

0000

BIT 21

PARTITION 1

0001

BIT 21

PARTITION 2

0010

BIT 21

PARTITION 3

0011

BIT 22

PARTITION 4

0100

BIT 22

PARTITION 5

0101

BIT 22

PARTITION 6

0110

BIT 22

PARTITION 7

0111

BIT 23

PARTITION 8

1000

BIT 23

PARTITION 9

1001

BIT 23

PARTITION 10

1010

BIT 23

PARTITION 11

1011

BIT 24

PARTITION 12

1100

BIT 24

PARTITION 13

1101

BIT 24

PARTITION 14

1110

BIT 24

PARTITION 15

1111

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