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SAM0462-031704
ESS Technology, Inc.
ES6028 PRODUCT BRIEF
ES6028 PIN DESCRIPTION
TSD0
33
O
Audio transmit serial data output 0.
SEL_PLL0
I
Refer to the description and matrix for SEL_PLL2 pin 32.
TSD1
36
O
Audio transmit serial data output 1.
SEL_PLL1
I
Refer to the description and matrix for SEL_PLL2 pin 32.
TSD2
37
O
Audio transmit serial data output 2.
NC
38, 42, 48
—
No connect pins. Leave open.
MCLK
39
I/O
Audio master clock for audio DAC.
TBCK
40
I/O
Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
SPDIF
41
O
S/PDIF output.
SEL_PLL3
I
Clock source select. Strapped to VCC or ground via 4.7-k
Ω resistor; read only
during reset.
RSD
45
I
Audio receive serial data.
RWS
46
I
Audio receive frame sync.
RBCK
47
I
Audio receive bit clock.
XIN
49
I
27-MHz crystal input.
XOUT
50
O
27-MHz crystal output.
AVEE
51
P
Analog power for PLL.
AVSS
52
G
Analog ground for PLL.
DMA[11:0]
53-58, 61-66
O
DRAM address bus.
DCAS#
69
O
DRAM column address strobe.
DOE#
70
O
DRAM output enable.
DSCK_EN
O
DRAM clock enable.
DWE#
71
O
DRAM write enable.
DRAS#
72
O
DRAM row address strobe.
DMBS0
73
O
SDRAM bank select 0.
DMBS1
74
O
SDRAM bank select 1.
DB[15:0]
77-82, 85-90, 93-96
I/O
DRAM data bus.
DCS[1:0]#
97,100
O
SDRAM chip select.
DQM
101
O
Data input/output mask.
DSCK
102
O
Output clock to SDRAM.
Table 1
ES6028 Pin Description (Continued)
Name
Pin Numbers
I/O
Definition
SEL_PLL3
Clock Source
0
Crystal oscillator
1
DCLK input
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