IRC1802 datasheet(2/4 Pages) INFINEON

2 / 4 page

The IRC1802 is a low-cost, highly inte-

grated SIR, MIR, FIR and Very Fast Infrared

(VFIR) communications

controller capable of supporting IrDA 1.x

infrared modulation schemes including HP-

SIR and Sharp ASK. The IrDA 1.x low and

high-speed communication modes support

all speeds up to 16 Mb/s (VFIR). All

speeds can use Direct Memory Access.

The same drivers are used for all speeds

for receiving and transmitting, simplifying

driver programming and speed upgrades.

Typical applications include data transfer

in notebook computers, desktops comput-

ers, printers, access-points, digital cameras

and peer-peer or client-server network

environments.

Architecture

The IRC1802 Infrared Communications

Controller consists of an Infrared Core

module and a Host Interface module (see

IRC 1802 Block Diagram).

The Infrared Core module controls all

infrared communication functions. It is

divided into four subsystems: SIR, MIR,

FIR and Very Fast Infrared (VFIR). Each

subsystem consists of a controller and a

modem.

The SIR subsystem improves on the

popular 16550 UART scheme by combining

a high performance DMA asynchronous

receiver-transmitter with the hardware Link

Access Protocol (IrLAP) for a complete

hardware SIR packet transfer.

Features

s IrDA 1.x, HP-SIR, and Sharp ASK

compliant

s Supports all IrDA data rates up to Very

Fast IR (VFIR), 16 Mb/s

s High performance hardware based IrDA

SIR Link Access Protocol (IrLAP)

s Host Direct Memory Access (DMA) and

Shared Memory modes

s Burst packet transmission and recep-

tion for all data rates

s Hardware transceiver Serial Interface

(SIF) programming

s Direct interface connection to all

vendors Infrared Transceiver modules

s Support for dual channel transceivers

s General purpose I/O pins for external

device control

s ISA Plug and Play (PnP) and PCMCIA

bus interface

s Single 48 or 96 MHz external clock

input

s 3.3 V supply voltage

s Small 100-pin Thin Quad Flat Pack

(TQFP) package

The Host Interface module connects to an

ISA bus or PCMCIA bus. It contains the

bus interface logic, system configuration

registers, power management circuitry, and

local DMA control functions. The IRC1802

supports two modes of block data

transfer: Host DMA and Shared Memory

Buffer. In Host DMA mode, data is

transferred using the host system’s DMA

controller. In Shared Memory mode, data

is first buffered in local RAM, then read by

the host during receive-mode or shifted

out to the infrared link during transmit-

mode.

s Shared Memory and Host DMA modes

Shared Memory mode is a Local DMA

mode with 32 Kbytes SRAM locally.

In this mode, both the controller and

host have access to a shared block of

memory to which data can be read or

written. During packet transmitting or

receiving there is no data transfer on

the system bus.

For packet sending, the host copies the

packet to the Tx buffer of shared

memory, initializes the Transmit

Request and waits for the End of

Transmit, EOTR, condition to generate

an interrupt.

For packet receiving, the host waits for

the End of Receive, EOR, interrupt

condition and copies packets received

from the Rx buffer of shared memory.

The programming is simple and the

operation is fast.

s Burst packet transmission and recep-

tion support for all data rates Burst

data transfer consisting of multiple IrDA

frames are accomplished by adding

control headers to the desired outgoing

data frames and arranging them

sequentially in the transmit buffer of

the host’s or local shared memory.

The Tx and Rx Frame Control Modules

control transmit and receive functions.

The 32 Kbytes shared memory can

keep seven IrDA frames with size of

2048 bytes.

s Direct Interface to both Legacy

and Digital Serial Interface (SIF)

Transceivers

The Serial Interface (SIF) module allows

the controller to interface directly to

Infineon’s IRM1600

transceiver.

This transceiver supports new features

like speed mode select (VFIR), pro-

grammable modulation setting, LED

power control, receiver sensitivity and

power management.

Synchronous MACRO Bus Interface

Single / Dual Channel Transceiver Interface

Synchronous Bus boundary

Synchronous Ł

8 MHz Boundary

Tx Bus Mastering

and 16 x 8 FIFO

Tx Frame

Controller

Rx Bus Mastering

and 16 x 8 FIFO

access logic

Tx and Rx

Regs

Rx Frame

Controller

FIR

Cntl

VFIR

Cntl

MIR

Cntl

SIR

Cntl

SIR

Cntl

MIR

Cntl

VFIR

Cntl

FIR

Cntl

FIR

Dem

SIR Rx

VFIR FIR Rx

SD / CLK

VFIR

Dem

MIR

Dem

HP /

Sharp

Dem

FIR

Dem

VFIR

Mod

MIR

Mod

HP /

Sharp

Mod

Rx Data Interface

CRC

Chk

CRC

Gen

IRC 1802

IrDA Communications Controller

for SIR, MIR, FIR and VFIR

IR C 1802 BL OCK DIA GRAM

IRC1802 Datasheet(PDF) 2 Page - Infineon Technologies AG

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