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CY2273A
8
Switching Characteristics for CY2273A-3[8]Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
All
Output Duty Cycle[9]
t1 = t1A ÷ t1B
45
50
55
%
t2
CPUCLK,
IOAPIC
CPU and IOAPIC Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.75
1.0
4.0
V/ns
t2
REF0
USBCLK
REF0 and USBCLK Ris-
ing and Falling Edge Rate
Between 0.4V and 2.4V
1.0
4.0
V/ns
t2
SDRAM
PCI
SDRAM and PCI Clock
Rising and Falling Edge
Rate
Between 0.4V and 2.4V
0.85
1.0
4.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.67
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.67
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
Measured at 1.5V, VDDCPU = 3.3V
100
300
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
900
ps
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
600
ps
t8
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
500
ps
t10
CPUCLK,
SDRAM
Cycle-Cycle Clock Jitter
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
750
ps
t10
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
500
ps
t11
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, AGP, and SDRAM clock sta-
bilization from power-up
3
ms
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