µPD61P24

11

11.5

S-OUT Pin

By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that

communication is in progress.

The S-OUT pin is CMOS output.

The S-OUT pin goes high on reset.

11.6

S-IN Pin (D0 bit of P1)

To input serial data, use the S-IN pin. When control register (P1) is set to serial input mode, the S-IN pin is

connected as an input to the LSB of the accumulator; the S-IN pin is pulled down to the VSS level within the LSI.

In this state, if the rotate-left accumulator instruction (RL A) is executed, the data on the S-IN pin is copied to the

LSB of the accumulator.

If the control register is released from serial input mode, the S-IN pin goes into a high-impedance state, but no

through current flows internally. When the RL A instruction is executed, the MSB is copied to the LSB.

At reset (all cleared), the S-IN pin goes into a high-impedance state.

Figure 11-3. Configuration of the S-IN Pin

A 3

A 2

A 1

A 0

CY

Control register

S-IN